68   uint64_t getBinaryCodeForInstr(const MCInst &MI,
74   unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
81   uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85   bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92   uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98   uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103   uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108   uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113   uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119   uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125   uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131   uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
134   uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
137   uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
143   uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
146   uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
149   uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
156   uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
161   uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
167   uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
173   uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
179   uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
186   uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
191   uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,  in getLdStmModeOpValue()  argument
194     ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();  in getLdStmModeOpValue()
218   uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
223   uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
228   uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
233   uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
238   uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
244   uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
249   uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
254   uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
259   uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
264   unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,  in getCCOutOpValue()  argument
269     return MI.getOperand(Op).getReg() == ARM::CPSR;  in getCCOutOpValue()
273   unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,  in getSOImmOpValue()  argument
277     const MCOperand &MO = MI.getOperand(Op);  in getSOImmOpValue()
290       Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getSOImmOpValue()
308   unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,  in getT2SOImmOpValue()  argument
311     unsigned SoImm = MI.getOperand(Op).getImm();  in getT2SOImmOpValue()
317   unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
320   unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
323   unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
326   unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
331   unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
334   unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
337   unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
341   unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,  in getNEONVcvtImm32OpValue()  argument
344     return 64 - MI.getOperand(Op).getImm();  in getNEONVcvtImm32OpValue()
347   unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
351   unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
354   unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
357   unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
360   unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
363   unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
367   unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
370   unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
373   unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
376   unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
380   unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
384   unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
387   unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
390   unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
393   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
397   unsigned VFPThumb2PostEncoder(const MCInst &MI,
413   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
437 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,  in NEONThumb2DataIPostEncoder()  argument
457 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,  in NEONThumb2LoadStorePostEncoder()  argument
471 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,  in NEONThumb2DupPostEncoder()  argument
484 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,  in NEONThumb2V8PostEncoder()  argument
497 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,  in VFPThumb2PostEncoder()  argument
509 getMachineOpValue(const MCInst &MI, const MCOperand &MO,  in getMachineOpValue()  argument
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,  in EncodeAddrModeOpValues()  argument
541   const MCOperand &MO  = MI.getOperand(OpIdx);  in EncodeAddrModeOpValues()
542   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in EncodeAddrModeOpValues()
567 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getBranchTargetOpValue()  argument
571   const MCOperand &MO = MI.getOperand(OpIdx);  in getBranchTargetOpValue()
578   Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getBranchTargetOpValue()
605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbBLTargetOpValue()  argument
608   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbBLTargetOpValue()
610     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl,  in getThumbBLTargetOpValue()
618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbBLXTargetOpValue()  argument
621   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbBLXTargetOpValue()
623     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx,  in getThumbBLXTargetOpValue()
630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbBRTargetOpValue()  argument
633   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbBRTargetOpValue()
635     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br,  in getThumbBRTargetOpValue()
642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbBCCTargetOpValue()  argument
645   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbBCCTargetOpValue()
647     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc,  in getThumbBCCTargetOpValue()
654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbCBTargetOpValue()  argument
657   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbCBTargetOpValue()
659     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI);  in getThumbCBTargetOpValue()
664 static bool HasConditionalBranch(const MCInst &MI) {  in HasConditionalBranch()  argument
665   int NumOp = MI.getNumOperands();  in HasConditionalBranch()
668       const MCOperand &MCOp1 = MI.getOperand(i);  in HasConditionalBranch()
669       const MCOperand &MCOp2 = MI.getOperand(i + 1);  in HasConditionalBranch()
683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getBranchTargetOpValue()  argument
690       ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);  in getBranchTargetOpValue()
691   return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);  in getBranchTargetOpValue()
697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getARMBranchTargetOpValue()  argument
700   const MCOperand MO = MI.getOperand(OpIdx);  in getARMBranchTargetOpValue()
702     if (HasConditionalBranch(MI))  in getARMBranchTargetOpValue()
703       return ::getBranchTargetOpValue(MI, OpIdx,  in getARMBranchTargetOpValue()
705     return ::getBranchTargetOpValue(MI, OpIdx,  in getARMBranchTargetOpValue()
713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getARMBLTargetOpValue()  argument
716   const MCOperand MO = MI.getOperand(OpIdx);  in getARMBLTargetOpValue()
718     if (HasConditionalBranch(MI))  in getARMBLTargetOpValue()
719       return ::getBranchTargetOpValue(MI, OpIdx,   in getARMBLTargetOpValue()
721     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI);  in getARMBLTargetOpValue()
728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getARMBLXTargetOpValue()  argument
731   const MCOperand MO = MI.getOperand(OpIdx);  in getARMBLXTargetOpValue()
733     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);  in getARMBLXTargetOpValue()
741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,  in getUnconditionalBranchTargetOpValue()  argument
745   const MCOperand MO = MI.getOperand(OpIdx);  in getUnconditionalBranchTargetOpValue()
748     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI);  in getUnconditionalBranchTargetOpValue()
771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,  in getAdrLabelOpValue()  argument
774   const MCOperand MO = MI.getOperand(OpIdx);  in getAdrLabelOpValue()
776     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12,  in getAdrLabelOpValue()
812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,  in getT2AdrLabelOpValue()  argument
815   const MCOperand MO = MI.getOperand(OpIdx);  in getT2AdrLabelOpValue()
817     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,  in getT2AdrLabelOpValue()
832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbAdrLabelOpValue()  argument
835   const MCOperand MO = MI.getOperand(OpIdx);  in getThumbAdrLabelOpValue()
837     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10,  in getThumbAdrLabelOpValue()
845 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,  in getThumbAddrModeRegRegOpValue()  argument
851   const MCOperand &MO1 = MI.getOperand(OpIdx);  in getThumbAddrModeRegRegOpValue()
852   const MCOperand &MO2 = MI.getOperand(OpIdx + 1);  in getThumbAddrModeRegRegOpValue()
860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,  in getAddrModeImm12OpValue()  argument
869   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrModeImm12OpValue()
883       Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getAddrModeImm12OpValue()
899     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);  in getAddrModeImm12OpValue()
912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,  in getT2Imm8s4OpValue()  argument
924   int32_t Imm8 = MI.getOperand(OpIdx).getImm();  in getT2Imm8s4OpValue()
944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,  in getT2AddrModeImm8s4OpValue()  argument
953   const MCOperand &MO = MI.getOperand(OpIdx);  in getT2AddrModeImm8s4OpValue()
962     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getT2AddrModeImm8s4OpValue()
966     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);  in getT2AddrModeImm8s4OpValue()
985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,  in getT2AddrModeImm0_1020s4OpValue()  argument
990   const MCOperand &MO = MI.getOperand(OpIdx);  in getT2AddrModeImm0_1020s4OpValue()
991   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getT2AddrModeImm0_1020s4OpValue()
998 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,  in getHiLo16ImmOpValue()  argument
1003   const MCOperand &MO = MI.getOperand(OpIdx);  in getHiLo16ImmOpValue()
1041     Fixups.push_back(MCFixup::Create(0, E, Kind, MI.getLoc()));  in getHiLo16ImmOpValue()
1054 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,  in getLdStSORegOpValue()  argument
1057   const MCOperand &MO = MI.getOperand(OpIdx);  in getLdStSORegOpValue()
1058   const MCOperand &MO1 = MI.getOperand(OpIdx+1);  in getLdStSORegOpValue()
1059   const MCOperand &MO2 = MI.getOperand(OpIdx+2);  in getLdStSORegOpValue()
1088 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,  in getAddrMode2OpValue()  argument
1095   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrMode2OpValue()
1097   uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI);  in getAddrMode2OpValue()
1103 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,  in getAddrMode2OffsetOpValue()  argument
1109   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrMode2OffsetOpValue()
1110   const MCOperand &MO1 = MI.getOperand(OpIdx+1);  in getAddrMode2OffsetOpValue()
1126 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,  in getPostIdxRegOpValue()  argument
1131   const MCOperand &MO = MI.getOperand(OpIdx);  in getPostIdxRegOpValue()
1132   const MCOperand &MO1 = MI.getOperand(OpIdx+1);  in getPostIdxRegOpValue()
1138 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,  in getAddrMode3OffsetOpValue()  argument
1145   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrMode3OffsetOpValue()
1146   const MCOperand &MO1 = MI.getOperand(OpIdx+1);  in getAddrMode3OffsetOpValue()
1158 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,  in getAddrMode3OpValue()  argument
1166   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrMode3OpValue()
1167   const MCOperand &MO1 = MI.getOperand(OpIdx+1);  in getAddrMode3OpValue()
1168   const MCOperand &MO2 = MI.getOperand(OpIdx+2);  in getAddrMode3OpValue()
1177     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getAddrMode3OpValue()
1195 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,  in getAddrModeThumbSPOpValue()  argument
1200   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getAddrModeThumbSPOpValue()
1201   assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&  in getAddrModeThumbSPOpValue()
1211 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,  in getAddrModeISOpValue()  argument
1217   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrModeISOpValue()
1218   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getAddrModeISOpValue()
1226 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,  in getAddrModePCOpValue()  argument
1229   const MCOperand MO = MI.getOperand(OpIdx);  in getAddrModePCOpValue()
1231     return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI);  in getAddrModePCOpValue()
1237 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,  in getAddrMode5OpValue()  argument
1246   const MCOperand &MO = MI.getOperand(OpIdx);  in getAddrMode5OpValue()
1259     Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));  in getAddrMode5OpValue()
1263     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);  in getAddrMode5OpValue()
1276 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,  in getSORegRegOpValue()  argument
1289   const MCOperand &MO  = MI.getOperand(OpIdx);  in getSORegRegOpValue()
1290   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getSORegRegOpValue()
1291   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);  in getSORegRegOpValue()
1324 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,  in getSORegImmOpValue()  argument
1335   const MCOperand &MO  = MI.getOperand(OpIdx);  in getSORegImmOpValue()
1336   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getSORegImmOpValue()
1371 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,  in getT2AddrModeSORegOpValue()  argument
1374   const MCOperand &MO1 = MI.getOperand(OpNum);  in getT2AddrModeSORegOpValue()
1375   const MCOperand &MO2 = MI.getOperand(OpNum+1);  in getT2AddrModeSORegOpValue()
1376   const MCOperand &MO3 = MI.getOperand(OpNum+2);  in getT2AddrModeSORegOpValue()
1390 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,  in getT2AddrModeImm8OpValue()  argument
1393   const MCOperand &MO1 = MI.getOperand(OpNum);  in getT2AddrModeImm8OpValue()
1394   const MCOperand &MO2 = MI.getOperand(OpNum+1);  in getT2AddrModeImm8OpValue()
1412 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,  in getT2AddrModeImm8OffsetOpValue()  argument
1415   const MCOperand &MO1 = MI.getOperand(OpNum);  in getT2AddrModeImm8OffsetOpValue()
1429 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,  in getT2AddrModeImm12OffsetOpValue()  argument
1432   const MCOperand &MO1 = MI.getOperand(OpNum);  in getT2AddrModeImm12OffsetOpValue()
1446 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,  in getT2SORegOpValue()  argument
1457   const MCOperand &MO  = MI.getOperand(OpIdx);  in getT2SORegOpValue()
1458   const MCOperand &MO1 = MI.getOperand(OpIdx + 1);  in getT2SORegOpValue()
1489 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,  in getBitfieldInvertedMaskOpValue()  argument
1494   const MCOperand &MO = MI.getOperand(Op);  in getBitfieldInvertedMaskOpValue()
1503 getRegisterListOpValue(const MCInst &MI, unsigned Op,  in getRegisterListOpValue()  argument
1512   unsigned Reg = MI.getOperand(Op).getReg();  in getRegisterListOpValue()
1521     unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;  in getRegisterListOpValue()
1528     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {  in getRegisterListOpValue()
1529       unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());  in getRegisterListOpValue()
1540 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,  in getAddrMode6AddressOpValue()  argument
1543   const MCOperand &Reg = MI.getOperand(Op);  in getAddrMode6AddressOpValue()
1544   const MCOperand &Imm = MI.getOperand(Op + 1);  in getAddrMode6AddressOpValue()
1564 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,  in getAddrMode6OneLane32AddressOpValue()  argument
1567   const MCOperand &Reg = MI.getOperand(Op);  in getAddrMode6OneLane32AddressOpValue()
1568   const MCOperand &Imm = MI.getOperand(Op + 1);  in getAddrMode6OneLane32AddressOpValue()
1591 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,  in getAddrMode6DupAddressOpValue()  argument
1594   const MCOperand &Reg = MI.getOperand(Op);  in getAddrMode6DupAddressOpValue()
1595   const MCOperand &Imm = MI.getOperand(Op + 1);  in getAddrMode6DupAddressOpValue()
1612 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,  in getAddrMode6OffsetOpValue()  argument
1615   const MCOperand &MO = MI.getOperand(Op);  in getAddrMode6OffsetOpValue()
1621 getShiftRight8Imm(const MCInst &MI, unsigned Op,  in getShiftRight8Imm()  argument
1624   return 8 - MI.getOperand(Op).getImm();  in getShiftRight8Imm()
1628 getShiftRight16Imm(const MCInst &MI, unsigned Op,  in getShiftRight16Imm()  argument
1631   return 16 - MI.getOperand(Op).getImm();  in getShiftRight16Imm()
1635 getShiftRight32Imm(const MCInst &MI, unsigned Op,  in getShiftRight32Imm()  argument
1638   return 32 - MI.getOperand(Op).getImm();  in getShiftRight32Imm()
1642 getShiftRight64Imm(const MCInst &MI, unsigned Op,  in getShiftRight64Imm()  argument
1645   return 64 - MI.getOperand(Op).getImm();  in getShiftRight64Imm()
1649 EncodeInstruction(const MCInst &MI, raw_ostream &OS,  in EncodeInstruction()  argument
1653   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());  in EncodeInstruction()
1664   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);  in EncodeInstruction()