Lines Matching refs:rz

290        FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
291        !strconcat(asmstr,  "\t$rz, $r32"), [], itin>;
298   FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
299                !strconcat(asmstr,  "\t$r32, $rz"), [], itin>;
315   MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316                !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
340   MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341                !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
362   FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
363             !strconcat(asmstr, "\t$rz, $ry"),
365   let Constraints = "$rx = $rz";
393   FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394          !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
574 // Format: ADDU rz, rx, ry MIPS16e
862 // Format: MOVE r32, rz MIPS16e
1269 // Format: SUBU rz, rx, ry MIPS16e