Lines Matching refs:pipeline

31 def P7_LS1    : FuncUnit; // Load/Store pipeline 1
32 def P7_LS2    : FuncUnit; // Load/Store pipeline 2
34 def P7_FX1    : FuncUnit; // FX pipeline 1
35 def P7_FX2    : FuncUnit; // FX pipeline 2
37 // VS pipeline 1 (vector integer ops. always here)
38 def P7_VS1    : FuncUnit; // VS pipeline 1
39 // VS pipeline 2 (128-bit stores and perms. here)
40 def P7_VS2    : FuncUnit; // VS pipeline 2
46 // Each LSU pipeline can also execute FX add and logical instructions.
47 // Each LSU pipeline can complete a load or store in one cycle.
57 // pipeline takes an additional cycle.
59 // The VSU XS is similar to the POWER6, but with a pipeline length of 2 cycles
65 // The VSU PM is similar to the POWER6, but with a pipeline length of 3 cycles
66 // (instead of 4 cycles on the POWER6). vsel is handled by the PM pipeline