Lines Matching refs:MVT
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, in allocateStack()
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentLoadRegType()
111 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
112 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
117 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
126 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
128 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
130 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
131 setOperationAction(ISD::FROUND, MVT::f32, Legal); in AMDGPUTargetLowering()
132 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
136 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
137 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
139 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
142 setOperationAction(ISD::STORE, MVT::i64, Promote); in AMDGPUTargetLowering()
143 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
145 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
146 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
148 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
149 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
151 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
152 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
154 setOperationAction(ISD::STORE, MVT::f64, Promote); in AMDGPUTargetLowering()
155 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64); in AMDGPUTargetLowering()
157 setOperationAction(ISD::STORE, MVT::v2f64, Promote); in AMDGPUTargetLowering()
158 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64); in AMDGPUTargetLowering()
162 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in AMDGPUTargetLowering()
165 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in AMDGPUTargetLowering()
167 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); in AMDGPUTargetLowering()
168 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); in AMDGPUTargetLowering()
169 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom); in AMDGPUTargetLowering()
173 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); in AMDGPUTargetLowering()
175 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in AMDGPUTargetLowering()
176 setTruncStoreAction(MVT::i64, MVT::i8, Expand); in AMDGPUTargetLowering()
177 setTruncStoreAction(MVT::i64, MVT::i1, Expand); in AMDGPUTargetLowering()
178 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand); in AMDGPUTargetLowering()
179 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand); in AMDGPUTargetLowering()
182 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
183 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
185 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
186 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
188 setOperationAction(ISD::LOAD, MVT::i64, Promote); in AMDGPUTargetLowering()
189 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
191 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
192 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
194 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
197 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
198 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
200 setOperationAction(ISD::LOAD, MVT::f64, Promote); in AMDGPUTargetLowering()
201 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); in AMDGPUTargetLowering()
203 setOperationAction(ISD::LOAD, MVT::v2f64, Promote); in AMDGPUTargetLowering()
204 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64); in AMDGPUTargetLowering()
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
217 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand); in AMDGPUTargetLowering()
218 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand); in AMDGPUTargetLowering()
219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand); in AMDGPUTargetLowering()
220 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand); in AMDGPUTargetLowering()
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand); in AMDGPUTargetLowering()
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand); in AMDGPUTargetLowering()
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
224 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
225 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand); in AMDGPUTargetLowering()
226 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand); in AMDGPUTargetLowering()
227 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand); in AMDGPUTargetLowering()
228 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand); in AMDGPUTargetLowering()
230 setOperationAction(ISD::BR_CC, MVT::i1, Expand); in AMDGPUTargetLowering()
233 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
234 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in AMDGPUTargetLowering()
235 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
236 setOperationAction(ISD::FFLOOR, MVT::f64, Custom); in AMDGPUTargetLowering()
241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in AMDGPUTargetLowering()
242 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in AMDGPUTargetLowering()
245 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in AMDGPUTargetLowering()
246 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering()
264 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in AMDGPUTargetLowering()
267 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in AMDGPUTargetLowering()
270 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
271 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AMDGPUTargetLowering()
272 setOperationAction(ISD::ROTR, MVT::i64, Expand); in AMDGPUTargetLowering()
274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); in AMDGPUTargetLowering()
275 setOperationAction(ISD::MUL, MVT::i64, Expand); in AMDGPUTargetLowering()
276 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
277 setOperationAction(ISD::MULHS, MVT::i64, Expand); in AMDGPUTargetLowering()
278 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
279 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
280 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
281 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
283 static const MVT::SimpleValueType VectorIntTypes[] = { in AMDGPUTargetLowering()
284 MVT::v2i32, MVT::v4i32 in AMDGPUTargetLowering()
287 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering()
329 static const MVT::SimpleValueType FloatVectorTypes[] = { in AMDGPUTargetLowering()
330 MVT::v2f32, MVT::v4f32 in AMDGPUTargetLowering()
333 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering()
359 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); in AMDGPUTargetLowering()
360 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); in AMDGPUTargetLowering()
389 MVT AMDGPUTargetLowering::getVectorIdxTy() const { in getVectorIdxTy()
390 return MVT::i32; in getVectorIdxTy()
401 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64); in isFPImmLegal()
407 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64); in ShouldShrinkFPConstant()
429 return VT == MVT::f32; in isFAbsFree()
434 return VT == MVT::f32; in isFNegFree()
461 return Src == MVT::i32 && Dest == MVT::i64; in isZExtFree()
495 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
632 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
656 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
706 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS); in LowerGlobalAddress()
707 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
938 DAG.getConstantFP(1.0f, MVT::f32), in LowerIntrinsicLRP()
959 if (VT != MVT::f32 || in CombineMinMax()
1033 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains) in SplitVectorLoad()
1061 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32); in MergeVectorStore()
1068 DAG.getConstant(i, MVT::i32)); in MergeVectorStore()
1069 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32); in MergeVectorStore()
1070 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg in MergeVectorStore()
1072 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32); in MergeVectorStore()
1073 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift); in MergeVectorStore()
1078 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt); in MergeVectorStore()
1110 Store->getValue(), DAG.getConstant(i, MVT::i32)); in SplitVectorStore()
1120 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains); in SplitVectorStore()
1134 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32, in LowerLOAD()
1149 assert(VT == MVT::i1 && "Only i1 non-extloads expected"); in LowerLOAD()
1157 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
1158 BasePtr, MVT::i8, MMO); in LowerLOAD()
1176 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1177 DAG.getConstant(2, MVT::i32)); in LowerLOAD()
1180 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2)); in LowerLOAD()
1184 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
1188 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), in LowerLOAD()
1189 DAG.getConstant(2, MVT::i32)); in LowerLOAD()
1192 DAG.getTargetConstant(0, MVT::i32), in LowerLOAD()
1194 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in LowerLOAD()
1196 DAG.getConstant(0x3, MVT::i32)); in LowerLOAD()
1197 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerLOAD()
1198 DAG.getConstant(3, MVT::i32)); in LowerLOAD()
1200 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt); in LowerLOAD()
1207 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode), in LowerLOAD()
1239 MemVT.bitsLT(MVT::i32)) { in LowerSTORE()
1241 if (Store->getMemoryVT() == MVT::i8) { in LowerSTORE()
1243 } else if (Store->getMemoryVT() == MVT::i16) { in LowerSTORE()
1247 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr, in LowerSTORE()
1248 DAG.getConstant(2, MVT::i32)); in LowerSTORE()
1249 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32, in LowerSTORE()
1250 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32)); in LowerSTORE()
1252 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr, in LowerSTORE()
1253 DAG.getConstant(0x3, MVT::i32)); in LowerSTORE()
1255 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerSTORE()
1256 DAG.getConstant(3, MVT::i32)); in LowerSTORE()
1258 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in LowerSTORE()
1263 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in LowerSTORE()
1266 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32), in LowerSTORE()
1268 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask, in LowerSTORE()
1269 DAG.getConstant(0xffffffff, MVT::i32)); in LowerSTORE()
1270 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in LowerSTORE()
1272 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in LowerSTORE()
1273 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, in LowerSTORE()
1274 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32)); in LowerSTORE()
1284 MVT INTTY; in LowerSDIV24()
1285 MVT FLTTY; in LowerSDIV24()
1287 INTTY = MVT::i32; in LowerSDIV24()
1288 FLTTY = MVT::f32; in LowerSDIV24()
1290 INTTY = MVT::v2i32; in LowerSDIV24()
1291 FLTTY = MVT::v2f32; in LowerSDIV24()
1293 INTTY = MVT::v4i32; in LowerSDIV24()
1294 FLTTY = MVT::v4f32; in LowerSDIV24()
1346 if (INTTY == MVT::i32) { in LowerSDIV24()
1432 if (OVT == MVT::i64) in LowerSDIV()
1435 if (OVT.getScalarType() == MVT::i32) in LowerSDIV()
1438 if (OVT == MVT::i16 || OVT == MVT::i8) { in LowerSDIV()
1515 if (OVT.getScalarType() == MVT::i64) in LowerSREM()
1518 if (OVT.getScalarType() == MVT::i32) in LowerSREM()
1674 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
1676 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64); in LowerFCEIL()
1677 const SDValue One = DAG.getConstantFP(1.0, MVT::f64); in LowerFCEIL()
1679 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); in LowerFCEIL()
1685 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
1686 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
1693 assert(Op.getValueType() == MVT::f64); in LowerFTRUNC()
1695 const SDValue Zero = DAG.getConstant(0, MVT::i32); in LowerFTRUNC()
1696 const SDValue One = DAG.getConstant(1, MVT::i32); in LowerFTRUNC()
1698 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
1702 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
1708 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32, in LowerFTRUNC()
1710 DAG.getConstant(FractBits - 32, MVT::i32), in LowerFTRUNC()
1711 DAG.getConstant(ExpBits, MVT::i32)); in LowerFTRUNC()
1712 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in LowerFTRUNC()
1713 DAG.getConstant(1023, MVT::i32)); in LowerFTRUNC()
1716 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32); in LowerFTRUNC()
1717 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
1720 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in LowerFTRUNC()
1722 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
1724 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
1726 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64); in LowerFTRUNC()
1728 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
1729 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
1730 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
1732 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32); in LowerFTRUNC()
1734 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32); in LowerFTRUNC()
1739 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
1740 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
1742 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
1749 assert(Op.getValueType() == MVT::f64); in LowerFRINT()
1752 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64); in LowerFRINT()
1753 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
1755 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
1756 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
1758 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
1761 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64); in LowerFRINT()
1763 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); in LowerFRINT()
1766 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFRINT()
1784 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
1786 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64); in LowerFFLOOR()
1787 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64); in LowerFFLOOR()
1789 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64); in LowerFFLOOR()
1795 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
1796 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
1803 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64) in LowerUINT_TO_FP()
1807 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, in LowerUINT_TO_FP()
1808 DAG.getConstant(0, MVT::i32)); in LowerUINT_TO_FP()
1809 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); in LowerUINT_TO_FP()
1810 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, in LowerUINT_TO_FP()
1811 DAG.getConstant(1, MVT::i32)); in LowerUINT_TO_FP()
1812 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi); in LowerUINT_TO_FP()
1813 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi, in LowerUINT_TO_FP()
1814 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32 in LowerUINT_TO_FP()
1815 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi); in LowerUINT_TO_FP()
1821 MVT VT = Op.getSimpleValueType(); in ExpandSIGN_EXTEND_INREG()
1833 MVT VT = Op.getSimpleValueType(); in LowerSIGN_EXTEND_INREG()
1834 MVT ScalarVT = VT.getScalarType(); in LowerSIGN_EXTEND_INREG()
1894 return DAG.getConstant(Result, MVT::i32); in constantFoldBFE()
1897 return DAG.getConstant(Src0 >> Offset, MVT::i32); in constantFoldBFE()
1915 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
1916 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32); in performMulCombine()
1917 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1); in performMulCombine()
1919 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32); in performMulCombine()
1920 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32); in performMulCombine()
1921 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1); in performMulCombine()
1961 return DAG.getConstant(0, MVT::i32); in PerformDAGCombine()
1988 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
2014 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32); in PerformDAGCombine()
2015 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()