Lines Matching refs:vaddr

31      SDTCisVT<3, i32>,    // vaddr(VGPR)
570    i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
573      #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
589                              (ins SReg_128:$srsrc, VReg_32:$vaddr,
597                              (ins SReg_128:$srsrc, VReg_32:$vaddr,
600 …                      asm#" $vdata, $srsrc + $vaddr + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
605                              (ins SReg_128:$srsrc, VReg_32:$vaddr,
608 …             asm#" $vdata, $srsrc[$vaddr] + $offset + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
613                              (ins SReg_128:$srsrc, VReg_64:$vaddr,
616 …        asm#" $vdata, $srsrc[$vaddr[0]] + $vaddr[1] + $soffset, glc=$glc, slc=$slc, tfe=$tfe", []>;
622                            (ins SReg_128:$srsrc, VReg_64:$vaddr, u16imm:$offset),
623                            asm#" $vdata, $srsrc + $vaddr + $offset",
625                                                   i64:$vaddr, u16imm:$offset)))]>;
632     MUBUF <op, (outs), (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
634           name#" $vdata, $srsrc + $vaddr + $offset",
635           [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, u16imm:$offset))]> {
655        i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
658      #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
675        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
678      #" $tfe, $lwe, $slc, $vaddr, $srsrc",
710        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
713      #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
748        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
751      #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",