Lines Matching refs:MVT
39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_f64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_f64()
81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
94 if (LocVT == MVT::i64 && Offset < 6*8) in CC_Sparc64_Full()
97 else if (LocVT == MVT::f64 && Offset < 16*8) in CC_Sparc64_Full()
100 else if (LocVT == MVT::f32 && Offset < 16*8) in CC_Sparc64_Full()
103 else if (LocVT == MVT::f128 && Offset < 16*8) in CC_Sparc64_Full()
116 if (LocVT == MVT::f32) in CC_Sparc64_Full()
126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Half()
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Half()
132 if (LocVT == MVT::f32 && Offset < 16*8) { in CC_Sparc64_Half()
139 if (LocVT == MVT::i32 && Offset < 6*8) { in CC_Sparc64_Half()
142 LocVT = MVT::i64; in CC_Sparc64_Half()
232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); in LowerReturn_32()
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_32()
264 RetOps.push_back(DAG.getConstant(8, MVT::i32)); in LowerReturn_64()
290 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
291 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
292 DAG.getConstant(32, MVT::i32)); in LowerReturn_64()
297 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
298 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
317 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn_64()
367 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
368 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
377 assert(VA.getLocVT() == MVT::f64); in LowerFormalArguments_32()
380 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); in LowerFormalArguments_32()
389 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
390 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
396 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); in LowerFormalArguments_32()
399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments_32()
406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_32()
407 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
409 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
423 assert(VA.getValVT() == MVT::f64); in LowerFormalArguments_32()
441 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments_32()
449 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, in LowerFormalArguments_32()
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments_32()
465 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
473 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, in LowerFormalArguments_32()
474 DAG.getConstant(Offset, MVT::i32)); in LowerFormalArguments_32()
475 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, in LowerFormalArguments_32()
492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments_32()
522 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); in LowerFormalArguments_32()
532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
571 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
573 DAG.getConstant(32, MVT::i32)); in LowerFormalArguments_64()
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); in LowerFormalArguments_64()
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
726 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); in LowerCall_32()
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
779 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
788 assert(VA.getLocVT() == MVT::f64); in LowerCall_32()
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
796 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
804 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); in LowerCall_32()
809 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, in LowerCall_32()
815 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, in LowerCall_32()
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
829 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
839 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
856 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
860 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); in LowerCall_32()
870 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
901 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); in LowerCall_32()
903 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); in LowerCall_32()
906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32()
911 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); in LowerCall_32()
1010 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
1024 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; in fixupVariableFloatArgs()
1031 if (ValTy == MVT::f64) in fixupVariableFloatArgs()
1034 IReg, MVT::i64, CCValAssign::BCvt); in fixupVariableFloatArgs()
1036 assert(ValTy == MVT::f128 && "Unexpected type!"); in fixupVariableFloatArgs()
1040 IReg, MVT::i128, CCValAssign::BCvt); in fixupVariableFloatArgs()
1119 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1120 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1126 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1127 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1144 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, in LowerCall_64()
1147 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, in LowerCall_64()
1159 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1160 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1161 DAG.getConstant(32, MVT::i32)); in LowerCall_64()
1167 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1169 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1195 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_64()
1263 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr) in LowerCall_64()
1289 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1291 DAG.getConstant(32, MVT::i32)); in LowerCall_64()
1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); in SparcTargetLowering()
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); in SparcTargetLowering()
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); in SparcTargetLowering()
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); in SparcTargetLowering()
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); in SparcTargetLowering()
1381 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); in SparcTargetLowering()
1382 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); in SparcTargetLowering()
1385 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in SparcTargetLowering()
1388 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in SparcTargetLowering()
1389 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in SparcTargetLowering()
1390 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in SparcTargetLowering()
1399 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1400 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1404 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1405 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1406 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1407 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1411 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1412 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1413 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1414 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1418 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1419 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1420 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1421 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1425 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1426 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1427 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1429 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1430 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1433 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1434 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1435 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1436 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1438 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1439 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1440 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1441 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1444 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1445 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1446 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1447 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1448 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1449 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1450 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1452 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1453 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1454 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1455 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1458 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1459 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1460 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1461 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1462 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1463 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1464 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1465 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1466 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1467 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1469 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1471 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1473 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1474 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); in SparcTargetLowering()
1475 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1476 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1477 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1478 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1487 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1488 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, in SparcTargetLowering()
1492 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1495 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1496 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1499 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1500 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1502 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1507 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1508 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1511 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1512 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1513 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1514 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1515 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1516 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1517 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1518 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1519 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1520 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1521 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1522 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1523 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1524 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1525 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1526 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1527 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1528 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in SparcTargetLowering()
1530 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1531 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1532 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1533 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1536 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1537 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1538 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1540 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1541 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1542 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1545 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1546 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1549 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1550 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1551 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1552 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1554 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1555 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1557 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1558 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1559 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1563 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1565 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1567 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1570 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1571 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1572 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1573 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1574 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1581 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1585 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1586 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1588 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1589 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1593 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1594 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1595 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1596 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1597 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1598 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1599 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1601 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1602 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1604 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1605 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1618 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1619 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1620 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1621 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1622 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1623 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1624 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1626 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1627 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1628 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1704 return MVT::i32; in getSetCCResultType()
1831 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); in makeAddress()
1840 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); in makeAddress()
1901 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerGlobalTLSAddress()
1932 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX in LowerGlobalTLSAddress()
2100 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2107 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2112 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2117 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2122 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2128 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2133 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2140 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2147 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); in LowerF128Compare()
2156 if (Op.getOperand(0).getValueType() == MVT::f64) in LowerF128_FPEXTEND()
2160 if (Op.getOperand(0).getValueType() == MVT::f32) in LowerF128_FPEXTEND()
2172 if (Op.getOperand(0).getValueType() != MVT::f128) in LowerF128_FPROUND()
2175 if (Op.getValueType() == MVT::f64) in LowerF128_FPROUND()
2178 if (Op.getValueType() == MVT::f32) in LowerF128_FPROUND()
2191 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_SINT()
2194 if (Op.getOperand(0).getValueType() == MVT::f128 in LowerFP_TO_SINT()
2196 const char *libName = TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_SINT()
2207 if (VT == MVT::i32) in LowerFP_TO_SINT()
2208 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); in LowerFP_TO_SINT()
2210 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); in LowerFP_TO_SINT()
2220 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2222 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2225 if (Op.getValueType() == MVT::f128 in LowerSINT_TO_FP()
2227 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2239 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2251 if (Op.getOperand(0).getValueType() != MVT::f128 || in LowerFP_TO_UINT()
2255 assert(VT == MVT::i32 || VT == MVT::i64); in LowerFP_TO_UINT()
2258 TLI.getLibcallName(VT == MVT::i32 in LowerFP_TO_UINT()
2269 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2273 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
2277 TLI.getLibcallName(OpVT == MVT::i32 in LowerUINT_TO_FP()
2301 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2304 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; in LowerBR_CC()
2306 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerBR_CC()
2311 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerBR_CC()
2316 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, in LowerBR_CC()
2317 DAG.getConstant(SPCC, MVT::i32), CompareFlag); in LowerBR_CC()
2337 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2338 Opc = LHS.getValueType() == MVT::i32 ? in LowerSELECT_CC()
2342 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { in LowerSELECT_CC()
2347 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); in LowerSELECT_CC()
2353 DAG.getConstant(SPCC, MVT::i32), CompareFlag); in LowerSELECT_CC()
2426 dl, MVT::Other, DAG.getEntryNode()); in getFLUSHW()
2518 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); in LowerF64Op()
2526 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2528 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2531 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); in LowerF64Op()
2534 dl, MVT::f64), 0); in LowerF64Op()
2535 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2537 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2554 SDValue Hi64 = DAG.getLoad(MVT::f64, in LowerF128Load()
2564 SDValue Lo64 = DAG.getLoad(MVT::f64, in LowerF128Load()
2571 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); in LowerF128Load()
2572 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); in LowerF128Load()
2575 dl, MVT::f128); in LowerF128Load()
2577 MVT::f128, in LowerF128Load()
2582 MVT::f128, in LowerF128Load()
2588 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2599 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); in LowerF128Store()
2600 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); in LowerF128Store()
2604 MVT::f64, in LowerF128Store()
2609 MVT::f64, in LowerF128Store()
2634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2641 if (Op.getValueType() == MVT::f64) in LowerFNEGorFABS()
2643 if (Op.getValueType() != MVT::f128) in LowerFNEGorFABS()
2651 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2653 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
2656 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); in LowerFNEGorFABS()
2661 dl, MVT::f128), 0); in LowerFNEGorFABS()
2662 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
2664 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
2671 if (Op.getValueType() != MVT::i64) in LowerADDC_ADDE_SUBC_SUBE()
2676 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2677 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
2678 DAG.getConstant(32, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2679 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
2682 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2683 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
2684 DAG.getConstant(32, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2685 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
2698 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); in LowerADDC_ADDE_SUBC_SUBE()
2708 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2709 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
2710 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
2711 DAG.getConstant(32, MVT::i64)); in LowerADDC_ADDE_SUBC_SUBE()
2713 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2727 EVT VT = MVT::i64; in LowerUMULO_SMULO()
2728 EVT WideVT = MVT::i128; in LowerUMULO_SMULO()
2739 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
2751 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2753 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT), in LowerUMULO_SMULO()
3134 MVT VT) const { in getRegForInlineAsmConstraint()
3186 if (N->getOperand(0).getValueType() != MVT::f128 in ReplaceNodeResults()
3187 || N->getValueType(0) != MVT::i64) in ReplaceNodeResults()
3202 if (N->getValueType(0) != MVT::f128 in ReplaceNodeResults()
3203 || N->getOperand(0).getValueType() != MVT::i64) in ReplaceNodeResults()