Lines Matching refs:Op0
44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {} in Comparison()
47 SDValue Op0, Op1; member
1137 if (!C.Op0.hasOneUse() || in adjustSubwordCmp()
1138 C.Op0.getOpcode() != ISD::LOAD || in adjustSubwordCmp()
1143 auto *Load = cast<LoadSDNode>(C.Op0); in adjustSubwordCmp()
1188 if (C.Op0.getValueType() != MVT::i32 || in adjustSubwordCmp()
1190 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, in adjustSubwordCmp()
1228 if (C.Op0.getValueType() == MVT::f128) in shouldSwapCmpOperands()
1250 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) { in shouldSwapCmpOperands()
1269 unsigned Opcode0 = C.Op0.getOpcode(); in shouldSwapCmpOperands()
1276 C.Op0.getOperand(1).getOpcode() == ISD::Constant && in shouldSwapCmpOperands()
1277 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff) in shouldSwapCmpOperands()
1298 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) { in adjustForSubtraction()
1301 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) || in adjustForSubtraction()
1302 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) { in adjustForSubtraction()
1303 C.Op0 = SDValue(N, 0); in adjustForSubtraction()
1318 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) { in adjustForFNeg()
1321 C.Op0 = SDValue(N, 0); in adjustForFNeg()
1337 if (C.Op0.getOpcode() == ISD::SHL && in adjustForLTGFR()
1338 C.Op0.getValueType() == MVT::i64 && in adjustForLTGFR()
1341 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1)); in adjustForLTGFR()
1343 SDValue ShlOp0 = C.Op0.getOperand(0); in adjustForLTGFR()
1349 C.Op0 = SDValue(N, 0); in adjustForLTGFR()
1361 if (C.Op0.getOpcode() == ISD::TRUNCATE && in adjustICmpTruncate()
1362 C.Op0.getOperand(0).getOpcode() == ISD::LOAD && in adjustICmpTruncate()
1365 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0)); in adjustICmpTruncate()
1367 <= C.Op0.getValueType().getSizeInBits()) { in adjustICmpTruncate()
1371 C.Op0 = C.Op0.getOperand(0); in adjustICmpTruncate()
1372 C.Op1 = DAG.getConstant(0, C.Op0.getValueType()); in adjustICmpTruncate()
1502 if (C.Op0.getOpcode() == ISD::AND) { in adjustForTestUnderMask()
1503 NewC.Op0 = C.Op0.getOperand(0); in adjustForTestUnderMask()
1504 NewC.Op1 = C.Op0.getOperand(1); in adjustForTestUnderMask()
1513 if (NewC.Op0.getValueType() != MVT::i64 || in adjustForTestUnderMask()
1534 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits(); in adjustForTestUnderMask()
1537 NewC.Op0.getOpcode() == ISD::SHL && in adjustForTestUnderMask()
1538 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1543 NewC.Op0 = NewC.Op0.getOperand(0); in adjustForTestUnderMask()
1546 NewC.Op0.getOpcode() == ISD::SRL && in adjustForTestUnderMask()
1547 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
1552 NewC.Op0 = NewC.Op0.getOperand(0); in adjustForTestUnderMask()
1563 C.Op0 = NewC.Op0; in adjustForTestUnderMask()
1567 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType()); in adjustForTestUnderMask()
1577 if (C.Op0.getValueType().isFloatingPoint()) { in getCmp()
1591 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1))) in getCmp()
1606 std::swap(C.Op0, C.Op1); in getCmp()
1617 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1, in emitCmp()
1622 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1, in emitCmp()
1625 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1); in emitCmp()
1632 unsigned Extend, SDValue Op0, SDValue Op1, in lowerMUL_LOHI32() argument
1634 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0); in lowerMUL_LOHI32()
1636 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1); in lowerMUL_LOHI32()
1649 SDValue Op0, SDValue Op1, in lowerGR128Binary() argument
1651 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0); in lowerGR128Binary()
1752 if (isAbsolute(C.Op0, TrueOp, FalseOp)) in lowerSELECT_CC()
1754 if (isAbsolute(C.Op0, FalseOp, TrueOp)) in lowerSELECT_CC()
2090 SDValue Op0 = Op.getOperand(0); in lowerSDIVREM() local
2098 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0); in lowerSDIVREM()
2111 Op0, Op1, Ops[1], Ops[0]); in lowerSDIVREM()