60 namespace X86 {  namespace
85           (X86::Mode16Bit | X86::Mode32Bit | X86::Mode64Bit)) {  in X86GenericDisassembler()
86   case X86::Mode16Bit:  in X86GenericDisassembler()
89   case X86::Mode32Bit:  in X86GenericDisassembler()
92   case X86::Mode64Bit:  in X86GenericDisassembler()
175 #define ENTRY(x) X86::x,  in translateRegister()
228   X86::CS,
229   X86::SS,
230   X86::DS,
231   X86::ES,
232   X86::FS,
233   X86::GS
244     baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;  in translateSrcIndex()
246     baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;  in translateSrcIndex()
249     baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;  in translateSrcIndex()
269     baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;  in translateDstIndex()
271     baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;  in translateDstIndex()
274     baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;  in translateDstIndex()
330       if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&  in translateImmediate()
331           Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&  in translateImmediate()
332           Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&  in translateImmediate()
333           Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&  in translateImmediate()
334           Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&  in translateImmediate()
335           Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&  in translateImmediate()
336           Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&  in translateImmediate()
337           Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&  in translateImmediate()
338           Opcode != X86::VINSERTPSrr)  in translateImmediate()
359     mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));  in translateImmediate()
362     mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));  in translateImmediate()
365     mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));  in translateImmediate()
426     mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;  in translateRMRegister()
471         baseReg = MCOperand::CreateReg(X86::x); break;  in translateRMMemory()
486     bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||  in translateRMMemory()
487                        Opcode == X86::VGATHERDPDYrm ||  in translateRMMemory()
488                        Opcode == X86::VGATHERQPDrm ||  in translateRMMemory()
489                        Opcode == X86::VGATHERDPSrm ||  in translateRMMemory()
490                        Opcode == X86::VGATHERQPSrm ||  in translateRMMemory()
491                        Opcode == X86::VPGATHERDQrm ||  in translateRMMemory()
492                        Opcode == X86::VPGATHERDQYrm ||  in translateRMMemory()
493                        Opcode == X86::VPGATHERQQrm ||  in translateRMMemory()
494                        Opcode == X86::VPGATHERDDrm ||  in translateRMMemory()
495                        Opcode == X86::VPGATHERQDrm);  in translateRMMemory()
496     bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||  in translateRMMemory()
497                        Opcode == X86::VGATHERDPSYrm ||  in translateRMMemory()
498                        Opcode == X86::VGATHERQPSYrm ||  in translateRMMemory()
499                        Opcode == X86::VGATHERDPDZrm ||  in translateRMMemory()
500                        Opcode == X86::VPGATHERDQZrm ||  in translateRMMemory()
501                        Opcode == X86::VPGATHERQQYrm ||  in translateRMMemory()
502                        Opcode == X86::VPGATHERDDYrm ||  in translateRMMemory()
503                        Opcode == X86::VPGATHERQDYrm);  in translateRMMemory()
504     bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||  in translateRMMemory()
505                        Opcode == X86::VGATHERDPSZrm ||  in translateRMMemory()
506                        Opcode == X86::VGATHERQPSZrm ||  in translateRMMemory()
507                        Opcode == X86::VPGATHERQQZrm ||  in translateRMMemory()
508                        Opcode == X86::VPGATHERDDZrm ||  in translateRMMemory()
509                        Opcode == X86::VPGATHERQDZrm);  in translateRMMemory()
526         indexReg = MCOperand::CreateReg(X86::x); break;  in translateRMMemory()
552         baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6  in translateRMMemory()
560       baseReg = MCOperand::CreateReg(X86::BX);  in translateRMMemory()
561       indexReg = MCOperand::CreateReg(X86::SI);  in translateRMMemory()
564       baseReg = MCOperand::CreateReg(X86::BX);  in translateRMMemory()
565       indexReg = MCOperand::CreateReg(X86::DI);  in translateRMMemory()
568       baseReg = MCOperand::CreateReg(X86::BP);  in translateRMMemory()
569       indexReg = MCOperand::CreateReg(X86::SI);  in translateRMMemory()
572       baseReg = MCOperand::CreateReg(X86::BP);  in translateRMMemory()
573       indexReg = MCOperand::CreateReg(X86::DI);  in translateRMMemory()
587         baseReg = MCOperand::CreateReg(X86::x); break;   in translateRMMemory()
681   mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));  in translateFPRegister()
697   mcInst.addOperand(MCOperand::CreateReg(X86::K0 + maskRegNum));  in translateMaskRegister()
784     if(mcInst.getOpcode() == X86::REP_PREFIX)  in translateInstruction()
785       mcInst.setOpcode(X86::XRELEASE_PREFIX);  in translateInstruction()
786     else if(mcInst.getOpcode() == X86::REPNE_PREFIX)  in translateInstruction()
787       mcInst.setOpcode(X86::XACQUIRE_PREFIX);  in translateInstruction()