Lines Matching refs:X86
104 case X86::MOV32rr: in postRAConvertToLEA()
105 case X86::MOV64rr: { in postRAConvertToLEA()
109 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r in postRAConvertToLEA()
110 : X86::LEA64r)) in postRAConvertToLEA()
120 case X86::ADD64ri32: in postRAConvertToLEA()
121 case X86::ADD64ri8: in postRAConvertToLEA()
122 case X86::ADD64ri32_DB: in postRAConvertToLEA()
123 case X86::ADD64ri8_DB: in postRAConvertToLEA()
124 case X86::ADD32ri: in postRAConvertToLEA()
125 case X86::ADD32ri8: in postRAConvertToLEA()
126 case X86::ADD32ri_DB: in postRAConvertToLEA()
127 case X86::ADD32ri8_DB: in postRAConvertToLEA()
128 case X86::ADD16ri: in postRAConvertToLEA()
129 case X86::ADD16ri8: in postRAConvertToLEA()
130 case X86::ADD16ri_DB: in postRAConvertToLEA()
131 case X86::ADD16ri8_DB: in postRAConvertToLEA()
138 case X86::ADD16rr: in postRAConvertToLEA()
139 case X86::ADD16rr_DB: in postRAConvertToLEA()
236 MachineOperand &p = MI->getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
237 if (p.isReg() && p.getReg() != X86::ESP) { in processInstruction()
240 MachineOperand &q = MI->getOperand(AddrOffset + X86::AddrIndexReg); in processInstruction()
241 if (q.isReg() && q.getReg() != X86::ESP) { in processInstruction()
270 if (opcode != X86::LEA16r && opcode != X86::LEA32r && opcode != X86::LEA64r && in processInstructionForSLM()
271 opcode != X86::LEA64_32r) in processInstructionForSLM()
285 case X86::LEA16r: in processInstructionForSLM()
286 addrr_opcode = X86::ADD16rr; in processInstructionForSLM()
287 addri_opcode = X86::ADD16ri; in processInstructionForSLM()
289 case X86::LEA32r: in processInstructionForSLM()
290 addrr_opcode = X86::ADD32rr; in processInstructionForSLM()
291 addri_opcode = X86::ADD32ri; in processInstructionForSLM()
293 case X86::LEA64_32r: in processInstructionForSLM()
294 case X86::LEA64r: in processInstructionForSLM()
295 addrr_opcode = X86::ADD64rr; in processInstructionForSLM()
296 addri_opcode = X86::ADD64ri32; in processInstructionForSLM()