Lines Matching refs:v16i16
1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass); in resetOperationActions()
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in resetOperationActions()
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom); in resetOperationActions()
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom); in resetOperationActions()
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); in resetOperationActions()
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal); in resetOperationActions()
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal); in resetOperationActions()
1247 setOperationAction(ISD::MUL, MVT::v16i16, Legal); in resetOperationActions()
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal); in resetOperationActions()
1253 setOperationAction(ISD::MULHS, MVT::v16i16, Legal); in resetOperationActions()
1255 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom); in resetOperationActions()
1260 setOperationAction(ISD::ADD, MVT::v16i16, Custom); in resetOperationActions()
1265 setOperationAction(ISD::SUB, MVT::v16i16, Custom); in resetOperationActions()
1270 setOperationAction(ISD::MUL, MVT::v16i16, Custom); in resetOperationActions()
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom); in resetOperationActions()
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in resetOperationActions()
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) in isPSHUFHWMask()
3715 if (VT == MVT::v16i16) { in isPSHUFHWMask()
3732 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16)) in isPSHUFLWMask()
3744 if (VT == MVT::v16i16) { in isPSHUFLWMask()
4612 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && in getShufflePSHUFHWImmediate()
4636 assert((VT == MVT::v8i16 || VT == MVT::v16i16) && in getShufflePSHUFLWImmediate()
6425 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) { in PerformBUILD_VECTORCombine()
6469 VT == MVT::v16i16) && Subtarget->hasAVX()) { in PerformBUILD_VECTORCombine()
8025 if (!hasInt256 && VT == MVT::v16i16) in isBlendMask()
8584 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break; in RewriteAsNarrowerShuffle()
9219 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 || in NormalizeVectorShuffle()
9567 if (VT == MVT::v16i16 && Subtarget->hasInt256()) { in LowerVECTOR_SHUFFLE()
9651 if (!Subtarget->hasInt256() && VT == MVT::v16i16) in LowerVSELECTtoBlend()
9690 case MVT::v16i16: in LowerVSELECT()
11092 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) && in LowerAVXExtend()
12767 (VT != MVT::v16i16 || InVT != MVT::v16i8)) in LowerSIGN_EXTEND()
15220 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) || in LowerScalarImmediateShift()
15284 MVT::v16i16, R, ShiftAmt, in LowerScalarImmediateShift()
15297 MVT::v16i16, R, ShiftAmt, in LowerScalarImmediateShift()
15388 VT == MVT::v8i32 || VT == MVT::v16i16)) || in LowerScalarVariableShift()
15456 case MVT::v16i16: in LowerScalarVariableShift()
15467 case MVT::v16i16: in LowerScalarVariableShift()
15480 case MVT::v16i16: in LowerScalarVariableShift()
15561 (Subtarget->hasInt256() && VT == MVT::v16i16)) && in LowerShift()
15719 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16; in LowerShift()
15858 case MVT::v16i16: in LowerSIGN_EXTEND_INREG()
19100 case MVT::v16i16: in matchIntegerMINMAX()
19187 if (!Subtarget->hasInt256() && VT == MVT::v16i16) in TransformVSELECTtoBlendVECTOR_SHUFFLE()
19514 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) { in PerformSELECTCombine()
19728 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 && in PerformSELECTCombine()
20296 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16))) in performShiftToAllZeros()
21911 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in PerformAddCombine()
21944 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && in PerformSubCombine()
22639 case MVT::v16i16: in getRegForInlineAsmConstraint()