Lines Matching refs:X86
250 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
268 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
269 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
270 NewOpcode = X86::CBW; in SimplifyMOVSX()
272 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
273 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
274 NewOpcode = X86::CWDE; in SimplifyMOVSX()
276 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
277 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
278 NewOpcode = X86::CDQE; in SimplifyMOVSX()
301 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
302 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && in SimplifyShortMoveForm()
303 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && in SimplifyShortMoveForm()
304 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && in SimplifyShortMoveForm()
311 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
326 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in SimplifyShortMoveForm()
327 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || in SimplifyShortMoveForm()
328 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) in SimplifyShortMoveForm()
333 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); in SimplifyShortMoveForm()
342 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; in getRetOpcode()
390 case X86::LEA64_32r: in Lower()
391 case X86::LEA64r: in Lower()
392 case X86::LEA16r: in Lower()
393 case X86::LEA32r: in Lower()
395 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && in Lower()
397 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && in Lower()
401 case X86::MOV32ri64: in Lower()
402 OutMI.setOpcode(X86::MOV32ri); in Lower()
407 case X86::VMOVAPDrr: in Lower()
408 case X86::VMOVAPDYrr: in Lower()
409 case X86::VMOVAPSrr: in Lower()
410 case X86::VMOVAPSYrr: in Lower()
411 case X86::VMOVDQArr: in Lower()
412 case X86::VMOVDQAYrr: in Lower()
413 case X86::VMOVDQUrr: in Lower()
414 case X86::VMOVDQUYrr: in Lower()
415 case X86::VMOVUPDrr: in Lower()
416 case X86::VMOVUPDYrr: in Lower()
417 case X86::VMOVUPSrr: in Lower()
418 case X86::VMOVUPSYrr: { in Lower()
424 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
425 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
426 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
427 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
428 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
429 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
430 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
431 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
432 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; in Lower()
433 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; in Lower()
434 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; in Lower()
435 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; in Lower()
441 case X86::VMOVSDrr: in Lower()
442 case X86::VMOVSSrr: { in Lower()
448 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; in Lower()
449 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; in Lower()
459 case X86::TAILJMPr64: in Lower()
460 case X86::CALL64r: in Lower()
461 case X86::CALL64pcrel32: { in Lower()
470 case X86::EH_RETURN: in Lower()
471 case X86::EH_RETURN64: { in Lower()
478 case X86::TAILJMPr: in Lower()
479 case X86::TAILJMPd: in Lower()
480 case X86::TAILJMPd64: { in Lower()
484 case X86::TAILJMPr: Opcode = X86::JMP32r; break; in Lower()
485 case X86::TAILJMPd: in Lower()
486 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; in Lower()
499 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; in Lower()
500 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; in Lower()
501 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; in Lower()
502 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; in Lower()
503 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; in Lower()
504 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; in Lower()
505 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; in Lower()
506 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; in Lower()
507 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; in Lower()
513 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; in Lower()
514 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; in Lower()
515 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; in Lower()
516 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; in Lower()
517 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; in Lower()
518 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; in Lower()
519 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; in Lower()
520 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; in Lower()
521 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; in Lower()
522 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; in Lower()
523 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; in Lower()
524 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; in Lower()
525 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; in Lower()
526 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; in Lower()
527 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; in Lower()
528 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; in Lower()
529 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; in Lower()
534 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; in Lower()
535 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; in Lower()
536 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; in Lower()
537 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; in Lower()
538 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; in Lower()
539 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; in Lower()
540 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; in Lower()
541 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; in Lower()
550 case X86::MOV8mr_NOREX: in Lower()
551 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break; in Lower()
552 case X86::MOV8rm_NOREX: in Lower()
553 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break; in Lower()
554 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break; in Lower()
555 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break; in Lower()
556 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break; in Lower()
557 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break; in Lower()
559 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; in Lower()
560 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; in Lower()
561 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; in Lower()
562 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; in Lower()
563 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; in Lower()
564 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; in Lower()
565 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; in Lower()
566 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; in Lower()
567 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; in Lower()
568 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; in Lower()
569 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; in Lower()
570 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; in Lower()
571 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; in Lower()
572 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; in Lower()
573 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; in Lower()
574 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; in Lower()
575 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; in Lower()
576 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; in Lower()
577 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; in Lower()
578 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; in Lower()
579 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; in Lower()
580 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; in Lower()
581 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; in Lower()
582 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; in Lower()
583 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; in Lower()
584 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; in Lower()
585 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; in Lower()
586 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; in Lower()
587 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; in Lower()
588 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; in Lower()
589 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; in Lower()
590 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; in Lower()
591 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; in Lower()
592 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; in Lower()
593 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; in Lower()
594 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; in Lower()
597 case X86::MOVSX16rr8: in Lower()
598 case X86::MOVSX32rr16: in Lower()
599 case X86::MOVSX64rr32: in Lower()
610 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || in LowerTlsAddr()
611 MI.getOpcode() == X86::TLS_base_addr64; in LowerTlsAddr()
613 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; in LowerTlsAddr()
618 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); in LowerTlsAddr()
622 case X86::TLS_addr32: in LowerTlsAddr()
623 case X86::TLS_addr64: in LowerTlsAddr()
626 case X86::TLS_base_addr32: in LowerTlsAddr()
629 case X86::TLS_base_addr64: in LowerTlsAddr()
641 LEA.setOpcode(X86::LEA64r); in LowerTlsAddr()
642 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest in LowerTlsAddr()
643 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base in LowerTlsAddr()
649 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
650 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
651 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base in LowerTlsAddr()
657 LEA.setOpcode(X86::LEA32r); in LowerTlsAddr()
658 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
661 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index in LowerTlsAddr()
668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); in LowerTlsAddr()
669 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX), STI); in LowerTlsAddr()
670 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX), STI); in LowerTlsAddr()
680 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 in LowerTlsAddr()
681 : X86::CALLpcrel32) in LowerTlsAddr()
693 BaseReg = X86::RAX; ScaleVal = 1; in EmitNops()
696 case 1: NumBytes -= 1; Opc = X86::NOOP; break; in EmitNops()
697 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break; in EmitNops()
698 case 3: NumBytes -= 3; Opc = X86::NOOPL; break; in EmitNops()
699 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break; in EmitNops()
700 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8; in EmitNops()
701 IndexReg = X86::RAX; break; in EmitNops()
702 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8; in EmitNops()
703 IndexReg = X86::RAX; break; in EmitNops()
704 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break; in EmitNops()
705 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512; in EmitNops()
706 IndexReg = X86::RAX; break; in EmitNops()
707 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512; in EmitNops()
708 IndexReg = X86::RAX; break; in EmitNops()
709 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512; in EmitNops()
710 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNops()
720 case X86::NOOP: in EmitNops()
723 case X86::XCHG16ar: in EmitNops()
724 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); in EmitNops()
726 case X86::NOOPL: in EmitNops()
727 case X86::NOOPW: in EmitNops()
769 OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg) in LowerPATCHPOINT()
771 OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg), STI); in LowerPATCHPOINT()
791 case X86::Int_MemBarrier: in EmitInstruction()
796 case X86::EH_RETURN: in EmitInstruction()
797 case X86::EH_RETURN64: { in EmitInstruction()
804 case X86::TAILJMPr: in EmitInstruction()
805 case X86::TAILJMPd: in EmitInstruction()
806 case X86::TAILJMPd64: in EmitInstruction()
811 case X86::TLS_addr32: in EmitInstruction()
812 case X86::TLS_addr64: in EmitInstruction()
813 case X86::TLS_base_addr32: in EmitInstruction()
814 case X86::TLS_base_addr64: in EmitInstruction()
817 case X86::MOVPC32r: { in EmitInstruction()
828 EmitToStreamer(OutStreamer, MCInstBuilder(X86::CALLpcrel32) in EmitInstruction()
835 EmitToStreamer(OutStreamer, MCInstBuilder(X86::POP32r) in EmitInstruction()
840 case X86::ADD32ri: { in EmitInstruction()
866 EmitToStreamer(OutStreamer, MCInstBuilder(X86::ADD32ri) in EmitInstruction()
879 case X86::MORESTACK_RET: in EmitInstruction()
883 case X86::MORESTACK_RET_RESTORE_R10: in EmitInstruction()
886 EmitToStreamer(OutStreamer, MCInstBuilder(X86::MOV64rr) in EmitInstruction()
887 .addReg(X86::R10) in EmitInstruction()
888 .addReg(X86::RAX)); in EmitInstruction()
891 case X86::SEH_PushReg: in EmitInstruction()
895 case X86::SEH_SaveReg: in EmitInstruction()
900 case X86::SEH_SaveXMM: in EmitInstruction()
905 case X86::SEH_StackAlloc: in EmitInstruction()
909 case X86::SEH_SetFrame: in EmitInstruction()
914 case X86::SEH_PushFrame: in EmitInstruction()
918 case X86::SEH_EndPrologue: in EmitInstruction()