Lines Matching refs:OS
61 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
63 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
69 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
78 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
80 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
81 OS << "#undef GET_REGINFO_ENUM\n"; in runEnums()
83 OS << "namespace llvm {\n\n"; in runEnums()
85 OS << "class MCRegisterClass;\n" in runEnums()
90 OS << "namespace " << Namespace << " {\n"; in runEnums()
91 OS << "enum {\n NoRegister,\n"; in runEnums()
94 OS << " " << Registers[i]->getName() << " = " << in runEnums()
98 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
99 OS << "};\n"; in runEnums()
101 OS << "}\n"; in runEnums()
110 OS << "\n// Register classes\n"; in runEnums()
112 OS << "namespace " << Namespace << " {\n"; in runEnums()
113 OS << "enum {\n"; in runEnums()
115 if (i) OS << ",\n"; in runEnums()
116 OS << " " << RegisterClasses[i]->getName() << "RegClassID"; in runEnums()
117 OS << " = " << i; in runEnums()
119 OS << "\n };\n"; in runEnums()
121 OS << "}\n"; in runEnums()
128 OS << "\n// Register alternate name indices\n"; in runEnums()
130 OS << "namespace " << Namespace << " {\n"; in runEnums()
131 OS << "enum {\n"; in runEnums()
133 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
134 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
135 OS << "};\n"; in runEnums()
137 OS << "}\n"; in runEnums()
142 OS << "\n// Subregister indices\n"; in runEnums()
146 OS << "namespace " << Namespace << " {\n"; in runEnums()
147 OS << "enum {\n NoSubRegister,\n"; in runEnums()
149 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; in runEnums()
150 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
152 OS << "}\n"; in runEnums()
155 OS << "} // End llvm namespace \n"; in runEnums()
156 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
160 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
165 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
173 OS << " {0, 0"; in EmitRegUnitPressure()
177 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
180 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
182 OS << " {0, 0} };\n" in EmitRegUnitPressure()
194 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
200 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
205 OS << RU.Weight << ", "; in EmitRegUnitPressure()
207 OS << "0 };\n" in EmitRegUnitPressure()
211 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
214 OS << "}\n\n"; in EmitRegUnitPressure()
216 OS << "\n" in EmitRegUnitPressure()
221 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
226 OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n"; in EmitRegUnitPressure()
228 OS << " nullptr };\n" in EmitRegUnitPressure()
232 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
239 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
242 OS << " 0 };\n" in EmitRegUnitPressure()
249 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
263 OS << PSets[j] << ", "; in EmitRegUnitPressure()
266 OS << "-1, \t// #" << RCSetStarts[i] << " "; in EmitRegUnitPressure()
268 OS << RegBank.getRegClasses()[i]->getName(); in EmitRegUnitPressure()
270 OS << "inferred"; in EmitRegUnitPressure()
273 OS << "~" << RegBank.getRegSetAt(*PSetI).Name; in EmitRegUnitPressure()
276 OS << "\n "; in EmitRegUnitPressure()
279 OS << "-1 };\n\n"; in EmitRegUnitPressure()
281 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
286 OS << " static const unsigned RCSetStartTable[] = {\n "; in EmitRegUnitPressure()
288 OS << RCSetStarts[i] << ","; in EmitRegUnitPressure()
290 OS << "0 };\n" in EmitRegUnitPressure()
295 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
302 OS << " static const unsigned RUSetStartTable[] = {\n "; in EmitRegUnitPressure()
305 OS << RCSetStarts[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx] << ","; in EmitRegUnitPressure()
307 OS << "0 };\n" in EmitRegUnitPressure()
314 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, in EmitRegMappingTables() argument
344 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
349 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
350 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
351 OS << i << "Dwarf2L[]"; in EmitRegMappingTables()
354 OS << " = {\n"; in EmitRegMappingTables()
369 OS << " { " << I->first << "U, " << getQualifiedName(I->second) in EmitRegMappingTables()
372 OS << "};\n"; in EmitRegMappingTables()
374 OS << ";\n"; in EmitRegMappingTables()
379 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
382 OS << " = sizeof(" << Namespace in EmitRegMappingTables()
386 OS << ";\n\n"; in EmitRegMappingTables()
404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
406 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
408 OS << " = {\n"; in EmitRegMappingTables()
417 OS << " { " << getQualifiedName(I->first) << ", " << RegNo in EmitRegMappingTables()
420 OS << "};\n"; in EmitRegMappingTables()
422 OS << ";\n"; in EmitRegMappingTables()
427 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
430 OS << " = sizeof(" << Namespace in EmitRegMappingTables()
434 OS << ";\n\n"; in EmitRegMappingTables()
440 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, in EmitRegMapping() argument
459 OS << " switch ("; in EmitRegMapping()
461 OS << "DwarfFlavour"; in EmitRegMapping()
463 OS << "EHFlavour"; in EmitRegMapping()
464 OS << ") {\n" in EmitRegMapping()
469 OS << " case " << i << ":\n"; in EmitRegMapping()
470 OS << " "; in EmitRegMapping()
472 OS << "RI->"; in EmitRegMapping()
477 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
479 OS << "false"; in EmitRegMapping()
481 OS << "true"; in EmitRegMapping()
482 OS << ");\n"; in EmitRegMapping()
483 OS << " break;\n"; in EmitRegMapping()
485 OS << " }\n"; in EmitRegMapping()
490 OS << " switch ("; in EmitRegMapping()
492 OS << "DwarfFlavour"; in EmitRegMapping()
494 OS << "EHFlavour"; in EmitRegMapping()
495 OS << ") {\n" in EmitRegMapping()
500 OS << " case " << i << ":\n"; in EmitRegMapping()
501 OS << " "; in EmitRegMapping()
503 OS << "RI->"; in EmitRegMapping()
508 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
510 OS << "false"; in EmitRegMapping()
512 OS << "true"; in EmitRegMapping()
513 OS << ");\n"; in EmitRegMapping()
514 OS << " break;\n"; in EmitRegMapping()
516 OS << " }\n"; in EmitRegMapping()
522 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
531 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
545 void print(raw_ostream &OS) { in print() argument
546 printBitVectorAsHex(OS, Values, 8); in print()
550 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
551 OS << getEnumName(VT); in printSimpleValueType()
554 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
555 OS << Idx->EnumValue; in printSubRegIndex()
597 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
598 OS << Val; in printDiff16()
630 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
634 OS << "unsigned " << ClName in emitComposeSubRegIndices()
667 OS << " static const " << getMinimalTypeForRange(Rows.size()) in emitComposeSubRegIndices()
670 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
671 OS << "\n };\n"; in emitComposeSubRegIndices()
675 OS << " static const " << getMinimalTypeForRange(SubRegIndices.size()+1) in emitComposeSubRegIndices()
678 OS << " { "; in emitComposeSubRegIndices()
681 OS << Rows[r][i]->EnumValue << ", "; in emitComposeSubRegIndices()
683 OS << "0, "; in emitComposeSubRegIndices()
684 OS << "},\n"; in emitComposeSubRegIndices()
686 OS << " };\n\n"; in emitComposeSubRegIndices()
688 OS << " --IdxA; assert(IdxA < " << SubRegIndices.size() << ");\n" in emitComposeSubRegIndices()
691 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
693 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
694 OS << "}\n\n"; in emitComposeSubRegIndices()
701 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
703 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
705 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
706 OS << "#undef GET_REGINFO_MC_DESC\n"; in runMCDesc()
784 OS << "namespace llvm {\n\n"; in runMCDesc()
789 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
790 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
791 OS << "};\n\n"; in runMCDesc()
794 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
795 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
796 OS << "};\n\n"; in runMCDesc()
799 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
801 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
805 OS << " { " << (*SRI)->Offset << ", " in runMCDesc()
809 OS << "};\n\n"; in runMCDesc()
813 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; in runMCDesc()
814 RegStrings.emit(OS, printChar); in runMCDesc()
815 OS << "};\n\n"; in runMCDesc()
817 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
819 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n"; in runMCDesc()
824 OS << " { " << RegStrings.get(Reg->getName()) << ", " in runMCDesc()
830 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
834 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
839 OS << " { " << getQualifiedName(Roots.front()->TheDef); in runMCDesc()
841 OS << ", " << getQualifiedName(Roots[r]->TheDef); in runMCDesc()
842 OS << " },\n"; in runMCDesc()
844 OS << "};\n\n"; in runMCDesc()
849 OS << "namespace { // Register classes...\n"; in runMCDesc()
860 OS << " // " << Name << " Register Class...\n" in runMCDesc()
865 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
867 OS << "\n };\n\n"; in runMCDesc()
869 OS << " // " << Name << " Bit set.\n" in runMCDesc()
877 BVE.print(OS); in runMCDesc()
878 OS << "\n };\n\n"; in runMCDesc()
881 OS << "}\n\n"; in runMCDesc()
883 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
895 OS << " { " << '\"' << RC.getName() << "\", " in runMCDesc()
905 OS << "};\n\n"; in runMCDesc()
907 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
910 OS << "extern const uint16_t " << TargetName; in runMCDesc()
911 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
913 OS << " 0,\n"; in runMCDesc()
922 OS << " " << Value << ",\n"; in runMCDesc()
924 OS << "};\n"; // End of HW encoding table in runMCDesc()
927 OS << "static inline void Init" << TargetName in runMCDesc()
942 EmitRegMapping(OS, Regs, false); in runMCDesc()
944 OS << "}\n\n"; in runMCDesc()
946 OS << "} // End llvm namespace \n"; in runMCDesc()
947 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
951 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
953 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
955 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
956 OS << "#undef GET_REGINFO_HEADER\n"; in runTargetHeader()
961 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
963 OS << "namespace llvm {\n\n"; in runTargetHeader()
965 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
971 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
976 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
991 OS << "namespace " << RegisterClasses[0]->Namespace in runTargetHeader()
999 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1001 OS << "} // end of namespace " << TargetName << "\n\n"; in runTargetHeader()
1003 OS << "} // End llvm namespace \n"; in runTargetHeader()
1004 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1011 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1013 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1015 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1016 OS << "#undef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1018 OS << "namespace llvm {\n\n"; in runTargetDesc()
1021 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1045 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1046 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1047 OS << "};\n"; in runTargetDesc()
1050 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; in runTargetDesc()
1052 OS << SubRegIndices[i]->getName(); in runTargetDesc()
1054 OS << "\", \""; in runTargetDesc()
1056 OS << "\" };\n\n"; in runTargetDesc()
1059 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; in runTargetDesc()
1061 OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) in runTargetDesc()
1064 OS << " };\n\n"; in runTargetDesc()
1066 OS << "\n"; in runTargetDesc()
1070 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1099 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1100 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1112 OS << "\n "; in runTargetDesc()
1113 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1114 OS << "// " << Idx->getName(); in runTargetDesc()
1117 OS << "\n};\n\n"; in runTargetDesc()
1120 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1122 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1123 OS << "};\n\n"; in runTargetDesc()
1134 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1137 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1138 OS << " nullptr\n};\n\n"; in runTargetDesc()
1145 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1153 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1155 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1156 OS << " };\n"; in runTargetDesc()
1159 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1165 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1167 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1168 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1175 OS << "namespace " << RegisterClasses[0]->Namespace in runTargetDesc()
1180 OS << " extern const TargetRegisterClass " in runTargetDesc()
1188 OS << "NullRegClasses,\n "; in runTargetDesc()
1190 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1192 OS << "nullptr\n"; in runTargetDesc()
1194 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1195 OS << " };\n\n"; in runTargetDesc()
1198 OS << "}\n"; in runTargetDesc()
1201 OS << "\nnamespace {\n"; in runTargetDesc()
1202 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
1204 OS << " &" << RegisterClasses[i]->getQualifiedName() in runTargetDesc()
1206 OS << " };\n"; in runTargetDesc()
1207 OS << "}\n"; // End of anonymous namespace... in runTargetDesc()
1211 OS << "\nstatic const TargetRegisterInfoDesc " in runTargetDesc()
1213 OS << " { 0, 0 },\n"; in runTargetDesc()
1218 OS << " { "; in runTargetDesc()
1219 OS << Reg.CostPerUse << ", " in runTargetDesc()
1222 OS << "};\n"; // End of register descriptors... in runTargetDesc()
1228 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1232 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1238 OS << " static const uint8_t Table["; in runTargetDesc()
1240 OS << " static const uint16_t Table["; in runTargetDesc()
1243 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; in runTargetDesc()
1246 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1250 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() in runTargetDesc()
1253 OS << " 0,\t// " << Idx->getName() << "\n"; in runTargetDesc()
1255 OS << " },\n"; in runTargetDesc()
1257 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1264 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1267 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1268 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1269 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1270 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1271 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1272 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1274 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1276 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1278 OS << ClassName << "::\n" << ClassName in runTargetDesc()
1283 OS.write_hex(RegBank.CoveringLanes); in runTargetDesc()
1284 OS << ") {\n" in runTargetDesc()
1297 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1299 OS << "}\n\n"; in runTargetDesc()
1311 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1314 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1315 OS << "0 };\n"; in runTargetDesc()
1330 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1332 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1333 OS << "};\n"; in runTargetDesc()
1335 OS << "\n\n"; in runTargetDesc()
1337 OS << "} // End llvm namespace \n"; in runTargetDesc()
1338 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1341 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1346 runEnums(OS, Target, RegBank); in run()
1347 runMCDesc(OS, Target, RegBank); in run()
1348 runTargetHeader(OS, Target, RegBank); in run()
1349 runTargetDesc(OS, Target, RegBank); in run()
1354 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1355 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()