180                              SmallVectorImpl<MachineOperand> &Cond,  in AnalyzeBranch()  argument
216         Cond.push_back(predSet->getOperand(1));  in AnalyzeBranch()
217         Cond.push_back(predSet->getOperand(2));  in AnalyzeBranch()
218         Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));  in AnalyzeBranch()
240     Cond.push_back(predSet->getOperand(1));  in AnalyzeBranch()
241     Cond.push_back(predSet->getOperand(2));  in AnalyzeBranch()
242     Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));  in AnalyzeBranch()
264                             const SmallVectorImpl<MachineOperand> &Cond,  in InsertBranch()  argument
270     if (Cond.empty()) {  in InsertBranch()
277       PredSet->getOperand(2).setImm(Cond[1].getImm());  in InsertBranch()
288     PredSet->getOperand(2).setImm(Cond[1].getImm());  in InsertBranch()
404 R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const  in ReverseBranchCondition()
406   MachineOperand &MO = Cond[1];  in ReverseBranchCondition()
424   MachineOperand &MO2 = Cond[2];  in ReverseBranchCondition()