128                              target_ulong vaddr)  in tlb_unprotect_code_phys()  argument
152 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)  in tlb_set_dirty1()  argument
154     if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {  in tlb_set_dirty1()
155         tlb_entry->addr_write = vaddr;  in tlb_set_dirty1()
161 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)  in tlb_set_dirty()  argument
166     vaddr &= TARGET_PAGE_MASK;  in tlb_set_dirty()
167     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);  in tlb_set_dirty()
169         tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);  in tlb_set_dirty()
175 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,  in tlb_add_large_page()  argument
181         env->tlb_flush_addr = vaddr & mask;  in tlb_add_large_page()
189     while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {  in tlb_add_large_page()
199 void tlb_set_page(CPUArchState *env, target_ulong vaddr,  in tlb_set_page()  argument
215         tlb_add_large_page(env, vaddr, size);  in tlb_set_page()
226            vaddr, paddr, prot, mmu_idx, pd);  in tlb_set_page()
229     address = vaddr;  in tlb_set_page()
261         if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {  in tlb_set_page()
269     index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);  in tlb_set_page()
270     env->iotlb[mmu_idx][index] = iotlb - vaddr;  in tlb_set_page()
272     te->addend = addend - vaddr;  in tlb_set_page()