Lines Matching refs:XX
3352 # define XX(_n) *p++ = (_n) in emit_AMD64Instr() macro
3359 case Asse_MOV: /*movups*/ XX(rex); XX(0x0F); XX(0x10); break; in emit_AMD64Instr()
3360 case Asse_OR: XX(rex); XX(0x0F); XX(0x56); break; in emit_AMD64Instr()
3361 case Asse_XOR: XX(rex); XX(0x0F); XX(0x57); break; in emit_AMD64Instr()
3362 case Asse_AND: XX(rex); XX(0x0F); XX(0x54); break; in emit_AMD64Instr()
3363 case Asse_ANDN: XX(rex); XX(0x0F); XX(0x55); break; in emit_AMD64Instr()
3364 case Asse_PACKSSD: XX(0x66); XX(rex); XX(0x0F); XX(0x6B); break; in emit_AMD64Instr()
3365 case Asse_PACKSSW: XX(0x66); XX(rex); XX(0x0F); XX(0x63); break; in emit_AMD64Instr()
3366 case Asse_PACKUSW: XX(0x66); XX(rex); XX(0x0F); XX(0x67); break; in emit_AMD64Instr()
3367 case Asse_ADD8: XX(0x66); XX(rex); XX(0x0F); XX(0xFC); break; in emit_AMD64Instr()
3368 case Asse_ADD16: XX(0x66); XX(rex); XX(0x0F); XX(0xFD); break; in emit_AMD64Instr()
3369 case Asse_ADD32: XX(0x66); XX(rex); XX(0x0F); XX(0xFE); break; in emit_AMD64Instr()
3370 case Asse_ADD64: XX(0x66); XX(rex); XX(0x0F); XX(0xD4); break; in emit_AMD64Instr()
3371 case Asse_QADD8S: XX(0x66); XX(rex); XX(0x0F); XX(0xEC); break; in emit_AMD64Instr()
3372 case Asse_QADD16S: XX(0x66); XX(rex); XX(0x0F); XX(0xED); break; in emit_AMD64Instr()
3373 case Asse_QADD8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDC); break; in emit_AMD64Instr()
3374 case Asse_QADD16U: XX(0x66); XX(rex); XX(0x0F); XX(0xDD); break; in emit_AMD64Instr()
3375 case Asse_AVG8U: XX(0x66); XX(rex); XX(0x0F); XX(0xE0); break; in emit_AMD64Instr()
3376 case Asse_AVG16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE3); break; in emit_AMD64Instr()
3377 case Asse_CMPEQ8: XX(0x66); XX(rex); XX(0x0F); XX(0x74); break; in emit_AMD64Instr()
3378 case Asse_CMPEQ16: XX(0x66); XX(rex); XX(0x0F); XX(0x75); break; in emit_AMD64Instr()
3379 case Asse_CMPEQ32: XX(0x66); XX(rex); XX(0x0F); XX(0x76); break; in emit_AMD64Instr()
3380 case Asse_CMPGT8S: XX(0x66); XX(rex); XX(0x0F); XX(0x64); break; in emit_AMD64Instr()
3381 case Asse_CMPGT16S: XX(0x66); XX(rex); XX(0x0F); XX(0x65); break; in emit_AMD64Instr()
3382 case Asse_CMPGT32S: XX(0x66); XX(rex); XX(0x0F); XX(0x66); break; in emit_AMD64Instr()
3383 case Asse_MAX16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEE); break; in emit_AMD64Instr()
3384 case Asse_MAX8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDE); break; in emit_AMD64Instr()
3385 case Asse_MIN16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEA); break; in emit_AMD64Instr()
3386 case Asse_MIN8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDA); break; in emit_AMD64Instr()
3387 case Asse_MULHI16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE4); break; in emit_AMD64Instr()
3388 case Asse_MULHI16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE5); break; in emit_AMD64Instr()
3389 case Asse_MUL16: XX(0x66); XX(rex); XX(0x0F); XX(0xD5); break; in emit_AMD64Instr()
3390 case Asse_SHL16: XX(0x66); XX(rex); XX(0x0F); XX(0xF1); break; in emit_AMD64Instr()
3391 case Asse_SHL32: XX(0x66); XX(rex); XX(0x0F); XX(0xF2); break; in emit_AMD64Instr()
3392 case Asse_SHL64: XX(0x66); XX(rex); XX(0x0F); XX(0xF3); break; in emit_AMD64Instr()
3393 case Asse_SAR16: XX(0x66); XX(rex); XX(0x0F); XX(0xE1); break; in emit_AMD64Instr()
3394 case Asse_SAR32: XX(0x66); XX(rex); XX(0x0F); XX(0xE2); break; in emit_AMD64Instr()
3395 case Asse_SHR16: XX(0x66); XX(rex); XX(0x0F); XX(0xD1); break; in emit_AMD64Instr()
3396 case Asse_SHR32: XX(0x66); XX(rex); XX(0x0F); XX(0xD2); break; in emit_AMD64Instr()
3397 case Asse_SHR64: XX(0x66); XX(rex); XX(0x0F); XX(0xD3); break; in emit_AMD64Instr()
3398 case Asse_SUB8: XX(0x66); XX(rex); XX(0x0F); XX(0xF8); break; in emit_AMD64Instr()
3399 case Asse_SUB16: XX(0x66); XX(rex); XX(0x0F); XX(0xF9); break; in emit_AMD64Instr()
3400 case Asse_SUB32: XX(0x66); XX(rex); XX(0x0F); XX(0xFA); break; in emit_AMD64Instr()
3401 case Asse_SUB64: XX(0x66); XX(rex); XX(0x0F); XX(0xFB); break; in emit_AMD64Instr()
3402 case Asse_QSUB8S: XX(0x66); XX(rex); XX(0x0F); XX(0xE8); break; in emit_AMD64Instr()
3403 case Asse_QSUB16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE9); break; in emit_AMD64Instr()
3404 case Asse_QSUB8U: XX(0x66); XX(rex); XX(0x0F); XX(0xD8); break; in emit_AMD64Instr()
3405 case Asse_QSUB16U: XX(0x66); XX(rex); XX(0x0F); XX(0xD9); break; in emit_AMD64Instr()
3406 case Asse_UNPCKHB: XX(0x66); XX(rex); XX(0x0F); XX(0x68); break; in emit_AMD64Instr()
3407 case Asse_UNPCKHW: XX(0x66); XX(rex); XX(0x0F); XX(0x69); break; in emit_AMD64Instr()
3408 case Asse_UNPCKHD: XX(0x66); XX(rex); XX(0x0F); XX(0x6A); break; in emit_AMD64Instr()
3409 case Asse_UNPCKHQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6D); break; in emit_AMD64Instr()
3410 case Asse_UNPCKLB: XX(0x66); XX(rex); XX(0x0F); XX(0x60); break; in emit_AMD64Instr()
3411 case Asse_UNPCKLW: XX(0x66); XX(rex); XX(0x0F); XX(0x61); break; in emit_AMD64Instr()
3412 case Asse_UNPCKLD: XX(0x66); XX(rex); XX(0x0F); XX(0x62); break; in emit_AMD64Instr()
3413 case Asse_UNPCKLQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6C); break; in emit_AMD64Instr()
3418 # undef XX in emit_AMD64Instr()