Lines Matching refs:vassert
83 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegMIPS()
90 vassert(r >= 0 && r < 32); in ppHRegMIPS()
95 vassert (r >= 0 && r < 32); in ppHRegMIPS()
100 vassert(r >= 0 && r < 32); in ppHRegMIPS()
105 vassert(r >= 0 && r < 32); in ppHRegMIPS()
610 vassert(i == *nregs); in getAllocableRegs_MIPS()
1014 vassert(imm16 != 0x8000); in MIPSRH_Imm()
1015 vassert(syned == True || syned == False); in MIPSRH_Imm()
1122 vassert(immR == False); /*there's no nor with an immediate operand!? */ in showMIPSAluOp()
1305 vassert(0 == (argiregs & ~mask)); in MIPSInstr_Call()
1306 vassert(is_sane_RetLoc(rloc)); in MIPSInstr_Call()
1323 vassert(0 == (argiregs & ~mask)); in MIPSInstr_CallAlways()
1324 vassert(is_sane_RetLoc(rloc)); in MIPSInstr_CallAlways()
1367 vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); in MIPSInstr_Load()
1370 vassert(mode64); in MIPSInstr_Load()
1381 vassert(sz == 1 || sz == 2 || sz == 4 || sz == 8); in MIPSInstr_Store()
1384 vassert(mode64); in MIPSInstr_Store()
1395 vassert(sz == 4 || sz == 8); in MIPSInstr_LoadL()
1398 vassert(mode64); in MIPSInstr_LoadL()
1409 vassert(sz == 4 || sz == 8); in MIPSInstr_StoreC()
1412 vassert(mode64); in MIPSInstr_StoreC()
1466 vassert(sz == 4 || sz == 8); in MIPSInstr_FpLdSt()
2031 vassert(0 == (argir & ~((1 << 4) | (1 << 5) | (1 << 6) in getRegUsage_MIPSInstr()
2320 vassert(offsetB >= 0); in genSpill_MIPS()
2321 vassert(!hregIsVirtual(rreg)); in genSpill_MIPS()
2327 vassert(mode64); in genSpill_MIPS()
2331 vassert(!mode64); in genSpill_MIPS()
2335 vassert(!mode64); in genSpill_MIPS()
2352 vassert(!hregIsVirtual(rreg)); in genReload_MIPS()
2357 vassert(mode64); in genReload_MIPS()
2361 vassert(!mode64); in genReload_MIPS()
2385 vassert(hregClass(r) == (mode64 ? HRcInt64 : HRcInt32)); in iregNo()
2386 vassert(!hregIsVirtual(r)); in iregNo()
2388 vassert(n <= 32); in iregNo()
2395 vassert(!hregIsVirtual(r)); in fregNo()
2397 vassert(n <= 31); in fregNo()
2404 vassert(!hregIsVirtual(r)); in dregNo()
2406 vassert(n <= 31); in dregNo()
2453 vassert(opc < 0x40); in mkFormI()
2454 vassert(rs < 0x20); in mkFormI()
2455 vassert(rt < 0x20); in mkFormI()
2474 vassert(opc < 0x40); in mkFormR()
2475 vassert(rs < 0x20); in mkFormR()
2476 vassert(rt < 0x20); in mkFormR()
2477 vassert(rd < 0x20); in mkFormR()
2478 vassert(sa < 0x20); in mkFormR()
2490 vassert(opc1 <= 0x3F); in mkFormS()
2491 vassert(rRD < 0x20); in mkFormS()
2492 vassert(rRS < 0x20); in mkFormS()
2493 vassert(rRT < 0x20); in mkFormS()
2494 vassert(opc2 <= 0x3F); in mkFormS()
2495 vassert(sa >= 0 && sa <= 0x3F); in mkFormS()
2507 vassert(am->tag == Mam_IR); in doAMode_IR()
2508 vassert(am->Mam.IR.index < 0x10000); in doAMode_IR()
2547 vassert(am->tag == Mam_RR); in doAMode_RR()
2599 vassert(r_dst < 0x20); in mkLoadImm()
2619 vassert(mode64); in mkLoadImm()
2644 vassert(r_dst < 0x20); in mkLoadImm_EXACTLY2or6()
2664 vassert(mode64); in mkLoadImm_EXACTLY2or6()
2686 vassert(r_dst < 0x20); in isLoadImm_EXACTLY2or6()
2704 vassert(p == (UChar*)&expect[2]); in isLoadImm_EXACTLY2or6()
2723 vassert(p == (UChar*)&expect[6]); in isLoadImm_EXACTLY2or6()
2747 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_machine_word()
2754 vassert(0); in do_load_or_store_machine_word()
2757 vassert(0); in do_load_or_store_machine_word()
2764 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_machine_word()
2771 vassert(0); in do_load_or_store_machine_word()
2774 vassert(0); in do_load_or_store_machine_word()
2790 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_word32()
2797 vassert(0); in do_load_or_store_word32()
2800 vassert(0); in do_load_or_store_word32()
2807 vassert(0 == (am->Mam.IR.index & 3)); in do_load_or_store_word32()
2814 vassert(0); in do_load_or_store_word32()
2817 vassert(0); in do_load_or_store_word32()
2827 vassert(r_dst < 0x20); in mkMoveReg()
2828 vassert(r_src < 0x20); in mkMoveReg()
2852 vassert(nbuf >= 32); in emit_MIPSInstr()
2870 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr()
2885 vassert(srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2886 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr()
2896 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2906 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2928 vassert(!immR); in emit_MIPSInstr()
2934 vassert(!srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2943 vassert(srcR->Mrh.Imm.syned); in emit_MIPSInstr()
2944 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr()
2980 vassert(sz32); in emit_MIPSInstr()
2986 vassert(n >= 0 && n <= 32); in emit_MIPSInstr()
2995 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
3012 vassert(n >= 0 && n < 32); in emit_MIPSInstr()
3022 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
3039 vassert(n >= 0 && n < 32); in emit_MIPSInstr()
3049 vassert((n >= 0 && n < 32) || (n > 31 && n < 64)); in emit_MIPSInstr()
3318 vassert(delta >= 20 && delta <= 32); in emit_MIPSInstr()
3333 vassert(disp_cp_chain_me_to_slowEP != NULL); in emit_MIPSInstr()
3334 vassert(disp_cp_chain_me_to_fastEP != NULL); in emit_MIPSInstr()
3343 vassert(i->Min.XDirect.cond != MIPScc_NV); in emit_MIPSInstr()
3378 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3397 vassert(disp_cp_xindir != NULL); in emit_MIPSInstr()
3405 vassert(i->Min.XIndir.cond != MIPScc_NV); in emit_MIPSInstr()
3428 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3446 vassert(i->Min.XAssisted.cond != MIPScc_NV); in emit_MIPSInstr()
3485 vassert(trcval != 0); in emit_MIPSInstr()
3500 vassert(delta > 0 && delta < 40); in emit_MIPSInstr()
3519 vassert(0 == (am_addr->Mam.IR.index & 3)); in emit_MIPSInstr()
3533 vassert(mode64); in emit_MIPSInstr()
3557 vassert(mode64); in emit_MIPSInstr()
3576 vassert(0 == (am_addr->Mam.IR.index & 3)); in emit_MIPSInstr()
3589 vassert(mode64); in emit_MIPSInstr()
3613 vassert(mode64); in emit_MIPSInstr()
3663 vassert(sz == 4 || sz == 8); in emit_MIPSInstr()
4034 vassert(mode64); in emit_MIPSInstr()
4047 vassert(mode64); in emit_MIPSInstr()
4121 vassert(evCheckSzB_MIPS() == (UChar*)p - (UChar*)p0); in emit_MIPSInstr()
4185 vassert(!(*is_profInc)); in emit_MIPSInstr()
4200 vassert(p - &buf[0] <= 128); in emit_MIPSInstr()
4230 vassert(0 == (3 & (HWord)p)); in chainXDirect_MIPS()
4231 vassert(isLoadImm_EXACTLY2or6(p, /*r*/9, in chainXDirect_MIPS()
4234 vassert(fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809); in chainXDirect_MIPS()
4235 vassert(fetch32(p + (mode64 ? 24 : 8) + 4) == 0x00000000); in chainXDirect_MIPS()
4254 vassert(len == (mode64 ? 32 : 16)); /* stay sane */ in chainXDirect_MIPS()
4276 vassert(0 == (3 & (HWord)p)); in unchainXDirect_MIPS()
4277 vassert(isLoadImm_EXACTLY2or6(p, /*r*/ 9, in unchainXDirect_MIPS()
4280 vassert(fetch32(p + (mode64 ? 24 : 8) + 0) == 0x120F809); in unchainXDirect_MIPS()
4281 vassert(fetch32(p + (mode64 ? 24 : 8) + 4) == 0x00000000); in unchainXDirect_MIPS()
4298 vassert(len == (mode64 ? 32 : 16)); /* stay sane */ in unchainXDirect_MIPS()
4309 vassert(sizeof(ULong*) == 8); in patchProfInc_MIPS()
4311 vassert(sizeof(ULong*) == 4); in patchProfInc_MIPS()
4313 vassert(0 == (3 & (HWord)p)); in patchProfInc_MIPS()
4314 vassert(isLoadImm_EXACTLY2or6((UChar *)p, /*r*/9, in patchProfInc_MIPS()
4319 vassert(fetch32(p + 24 + 0) == 0xDD280000); in patchProfInc_MIPS()
4320 vassert(fetch32(p + 24 + 4) == 0x65080001); in patchProfInc_MIPS()
4321 vassert(fetch32(p + 24 + 8) == 0xFD280000); in patchProfInc_MIPS()
4323 vassert(fetch32(p + 8 + 0) == 0x8D280000); in patchProfInc_MIPS()
4324 vassert(fetch32(p + 8 + 4) == 0x25080001); in patchProfInc_MIPS()
4325 vassert(fetch32(p + 8 + 8) == 0xAD280000); in patchProfInc_MIPS()
4326 vassert(fetch32(p + 8 + 12) == 0x2d010001); in patchProfInc_MIPS()
4327 vassert(fetch32(p + 8 + 16) == 0x8d280004); in patchProfInc_MIPS()
4328 vassert(fetch32(p + 8 + 20) == 0x01014021); in patchProfInc_MIPS()
4329 vassert(fetch32(p + 8 + 24) == 0xad280004); in patchProfInc_MIPS()