1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
32 using namespace llvm;
33
34
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
38
CC_Sparc_Assign_SRet(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
42 {
43 assert (ArgFlags.isSRet());
44
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
47 0,
48 LocVT, LocInfo));
49 return true;
50 }
51
CC_Sparc_Assign_f64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
55 {
56 static const MCPhysReg RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58 };
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62 } else {
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
66 LocVT, LocInfo));
67 return true;
68 }
69
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList, 6))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73 else
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
76 LocVT, LocInfo));
77 return true;
78 }
79
80 // Allocate a full-sized argument for the 64-bit ABI.
CC_Sparc64_Full(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128
85 || LocVT.getSizeInBits() == 64) &&
86 "Can't handle non-64 bits locations");
87
88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91 unsigned Offset = State.AllocateStack(size, alignment);
92 unsigned Reg = 0;
93
94 if (LocVT == MVT::i64 && Offset < 6*8)
95 // Promote integers to %i0-%i5.
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT == MVT::f64 && Offset < 16*8)
98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT == MVT::f32 && Offset < 16*8)
101 // Promote floats to %f1, %f3, ...
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT == MVT::f128 && Offset < 16*8)
104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105 Reg = SP::Q0 + Offset/16;
106
107 // Promote to register when possible, otherwise use the stack slot.
108 if (Reg) {
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
110 return true;
111 }
112
113 // This argument goes on the stack in an 8-byte slot.
114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116 if (LocVT == MVT::f32)
117 Offset += 4;
118
119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
120 return true;
121 }
122
123 // Allocate a half-sized argument for the 64-bit ABI.
124 //
125 // This is used when passing { float, int } structs by value in registers.
CC_Sparc64_Half(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130 unsigned Offset = State.AllocateStack(4, 4);
131
132 if (LocVT == MVT::f32 && Offset < 16*8) {
133 // Promote floats to %f0-%f31.
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
135 LocVT, LocInfo));
136 return true;
137 }
138
139 if (LocVT == MVT::i32 && Offset < 6*8) {
140 // Promote integers to %i0-%i5, using half the register.
141 unsigned Reg = SP::I0 + Offset/8;
142 LocVT = MVT::i64;
143 LocInfo = CCValAssign::AExt;
144
145 // Set the Custom bit if this i32 goes in the high bits of a register.
146 if (Offset % 8 == 0)
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
148 LocVT, LocInfo));
149 else
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
151 return true;
152 }
153
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
155 return true;
156 }
157
158 #include "SparcGenCallingConv.inc"
159
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
toCallerWindow(unsigned Reg)163 static unsigned toCallerWindow(unsigned Reg) {
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
167 return Reg;
168 }
169
170 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const171 SparcTargetLowering::LowerReturn(SDValue Chain,
172 CallingConv::ID CallConv, bool IsVarArg,
173 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<SDValue> &OutVals,
175 SDLoc DL, SelectionDAG &DAG) const {
176 if (Subtarget->is64Bit())
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
179 }
180
181 SDValue
LowerReturn_32(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const182 SparcTargetLowering::LowerReturn_32(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
188
189 // CCValAssign - represent the assignment of the return value to locations.
190 SmallVector<CCValAssign, 16> RVLocs;
191
192 // CCState - Info about the registers and stack slot.
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
194 DAG.getTarget(), RVLocs, *DAG.getContext());
195
196 // Analyze return values.
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
198
199 SDValue Flag;
200 SmallVector<SDValue, 4> RetOps(1, Chain);
201 // Make room for the return address offset.
202 RetOps.push_back(SDValue());
203
204 // Copy the result values into the output registers.
205 for (unsigned i = 0; i != RVLocs.size(); ++i) {
206 CCValAssign &VA = RVLocs[i];
207 assert(VA.isRegLoc() && "Can only return in registers!");
208
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
210 OutVals[i], Flag);
211
212 // Guarantee that all emitted copies are stuck together with flags.
213 Flag = Chain.getValue(1);
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
215 }
216
217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218 // If the function returns a struct, copy the SRetReturnReg to I0
219 if (MF.getFunction()->hasStructRetAttr()) {
220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
221 unsigned Reg = SFI->getSRetReturnReg();
222 if (!Reg)
223 llvm_unreachable("sret virtual register not created in the entry block");
224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
226 Flag = Chain.getValue(1);
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
228 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
229 }
230
231 RetOps[0] = Chain; // Update chain.
232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
233
234 // Add the flag if we have it.
235 if (Flag.getNode())
236 RetOps.push_back(Flag);
237
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
239 }
240
241 // Lower return values for the 64-bit ABI.
242 // Return values are passed the exactly the same way as function arguments.
243 SDValue
LowerReturn_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const244 SparcTargetLowering::LowerReturn_64(SDValue Chain,
245 CallingConv::ID CallConv, bool IsVarArg,
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
247 const SmallVectorImpl<SDValue> &OutVals,
248 SDLoc DL, SelectionDAG &DAG) const {
249 // CCValAssign - represent the assignment of the return value to locations.
250 SmallVector<CCValAssign, 16> RVLocs;
251
252 // CCState - Info about the registers and stack slot.
253 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
254 DAG.getTarget(), RVLocs, *DAG.getContext());
255
256 // Analyze return values.
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
258
259 SDValue Flag;
260 SmallVector<SDValue, 4> RetOps(1, Chain);
261
262 // The second operand on the return instruction is the return address offset.
263 // The return address is always %i7+8 with the 64-bit ABI.
264 RetOps.push_back(DAG.getConstant(8, MVT::i32));
265
266 // Copy the result values into the output registers.
267 for (unsigned i = 0; i != RVLocs.size(); ++i) {
268 CCValAssign &VA = RVLocs[i];
269 assert(VA.isRegLoc() && "Can only return in registers!");
270 SDValue OutVal = OutVals[i];
271
272 // Integer return values must be sign or zero extended by the callee.
273 switch (VA.getLocInfo()) {
274 case CCValAssign::Full: break;
275 case CCValAssign::SExt:
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
277 break;
278 case CCValAssign::ZExt:
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
280 break;
281 case CCValAssign::AExt:
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
283 break;
284 default:
285 llvm_unreachable("Unknown loc info!");
286 }
287
288 // The custom bit on an i32 return value indicates that it should be passed
289 // in the high bits of the register.
290 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
291 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
292 DAG.getConstant(32, MVT::i32));
293
294 // The next value may go in the low bits of the same register.
295 // Handle both at once.
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
297 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
298 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
299 // Skip the next value, it's already done.
300 ++i;
301 }
302 }
303
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
305
306 // Guarantee that all emitted copies are stuck together with flags.
307 Flag = Chain.getValue(1);
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
309 }
310
311 RetOps[0] = Chain; // Update chain.
312
313 // Add the flag if we have it.
314 if (Flag.getNode())
315 RetOps.push_back(Flag);
316
317 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
318 }
319
320 SDValue SparcTargetLowering::
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const321 LowerFormalArguments(SDValue Chain,
322 CallingConv::ID CallConv,
323 bool IsVarArg,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
325 SDLoc DL,
326 SelectionDAG &DAG,
327 SmallVectorImpl<SDValue> &InVals) const {
328 if (Subtarget->is64Bit())
329 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
330 DL, DAG, InVals);
331 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
332 DL, DAG, InVals);
333 }
334
335 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
336 /// passed in either one or two GPRs, including FP values. TODO: we should
337 /// pass FP values in FP registers for fastcc functions.
338 SDValue SparcTargetLowering::
LowerFormalArguments_32(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const339 LowerFormalArguments_32(SDValue Chain,
340 CallingConv::ID CallConv,
341 bool isVarArg,
342 const SmallVectorImpl<ISD::InputArg> &Ins,
343 SDLoc dl,
344 SelectionDAG &DAG,
345 SmallVectorImpl<SDValue> &InVals) const {
346 MachineFunction &MF = DAG.getMachineFunction();
347 MachineRegisterInfo &RegInfo = MF.getRegInfo();
348 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
349
350 // Assign locations to all of the incoming arguments.
351 SmallVector<CCValAssign, 16> ArgLocs;
352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
353 getTargetMachine(), ArgLocs, *DAG.getContext());
354 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
355
356 const unsigned StackOffset = 92;
357
358 unsigned InIdx = 0;
359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
360 CCValAssign &VA = ArgLocs[i];
361
362 if (Ins[InIdx].Flags.isSRet()) {
363 if (InIdx != 0)
364 report_fatal_error("sparc only supports sret on the first parameter");
365 // Get SRet from [%fp+64].
366 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
367 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
368 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
369 MachinePointerInfo(),
370 false, false, false, 0);
371 InVals.push_back(Arg);
372 continue;
373 }
374
375 if (VA.isRegLoc()) {
376 if (VA.needsCustom()) {
377 assert(VA.getLocVT() == MVT::f64);
378 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
379 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
380 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
381
382 assert(i+1 < e);
383 CCValAssign &NextVA = ArgLocs[++i];
384
385 SDValue LoVal;
386 if (NextVA.isMemLoc()) {
387 int FrameIdx = MF.getFrameInfo()->
388 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
389 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
390 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
391 MachinePointerInfo(),
392 false, false, false, 0);
393 } else {
394 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
395 &SP::IntRegsRegClass);
396 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
397 }
398 SDValue WholeValue =
399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
401 InVals.push_back(WholeValue);
402 continue;
403 }
404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
407 if (VA.getLocVT() == MVT::f32)
408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
409 else if (VA.getLocVT() != MVT::i32) {
410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
411 DAG.getValueType(VA.getLocVT()));
412 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
413 }
414 InVals.push_back(Arg);
415 continue;
416 }
417
418 assert(VA.isMemLoc());
419
420 unsigned Offset = VA.getLocMemOffset()+StackOffset;
421
422 if (VA.needsCustom()) {
423 assert(VA.getValVT() == MVT::f64);
424 // If it is double-word aligned, just load.
425 if (Offset % 8 == 0) {
426 int FI = MF.getFrameInfo()->CreateFixedObject(8,
427 Offset,
428 true);
429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
430 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
431 MachinePointerInfo(),
432 false,false, false, 0);
433 InVals.push_back(Load);
434 continue;
435 }
436
437 int FI = MF.getFrameInfo()->CreateFixedObject(4,
438 Offset,
439 true);
440 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
441 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
442 MachinePointerInfo(),
443 false, false, false, 0);
444 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
445 Offset+4,
446 true);
447 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
448
449 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
450 MachinePointerInfo(),
451 false, false, false, 0);
452
453 SDValue WholeValue =
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
456 InVals.push_back(WholeValue);
457 continue;
458 }
459
460 int FI = MF.getFrameInfo()->CreateFixedObject(4,
461 Offset,
462 true);
463 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
464 SDValue Load ;
465 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
466 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
467 MachinePointerInfo(),
468 false, false, false, 0);
469 } else {
470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
471 // Sparc is big endian, so add an offset based on the ObjectVT.
472 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
473 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
474 DAG.getConstant(Offset, MVT::i32));
475 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
476 MachinePointerInfo(),
477 VA.getValVT(), false, false,0);
478 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
479 }
480 InVals.push_back(Load);
481 }
482
483 if (MF.getFunction()->hasStructRetAttr()) {
484 // Copy the SRet Argument to SRetReturnReg.
485 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
486 unsigned Reg = SFI->getSRetReturnReg();
487 if (!Reg) {
488 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
489 SFI->setSRetReturnReg(Reg);
490 }
491 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
493 }
494
495 // Store remaining ArgRegs to the stack if this is a varargs function.
496 if (isVarArg) {
497 static const MCPhysReg ArgRegs[] = {
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
499 };
500 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
501 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
502 unsigned ArgOffset = CCInfo.getNextStackOffset();
503 if (NumAllocated == 6)
504 ArgOffset += StackOffset;
505 else {
506 assert(!ArgOffset);
507 ArgOffset = 68+4*NumAllocated;
508 }
509
510 // Remember the vararg offset for the va_start implementation.
511 FuncInfo->setVarArgsFrameOffset(ArgOffset);
512
513 std::vector<SDValue> OutChains;
514
515 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
517 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
519
520 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
521 true);
522 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
523
524 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
525 MachinePointerInfo(),
526 false, false, 0));
527 ArgOffset += 4;
528 }
529
530 if (!OutChains.empty()) {
531 OutChains.push_back(Chain);
532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
533 }
534 }
535
536 return Chain;
537 }
538
539 // Lower formal arguments for the 64 bit ABI.
540 SDValue SparcTargetLowering::
LowerFormalArguments_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const541 LowerFormalArguments_64(SDValue Chain,
542 CallingConv::ID CallConv,
543 bool IsVarArg,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
545 SDLoc DL,
546 SelectionDAG &DAG,
547 SmallVectorImpl<SDValue> &InVals) const {
548 MachineFunction &MF = DAG.getMachineFunction();
549
550 // Analyze arguments according to CC_Sparc64.
551 SmallVector<CCValAssign, 16> ArgLocs;
552 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
553 getTargetMachine(), ArgLocs, *DAG.getContext());
554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
555
556 // The argument array begins at %fp+BIAS+128, after the register save area.
557 const unsigned ArgArea = 128;
558
559 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
560 CCValAssign &VA = ArgLocs[i];
561 if (VA.isRegLoc()) {
562 // This argument is passed in a register.
563 // All integer register arguments are promoted by the caller to i64.
564
565 // Create a virtual register for the promoted live-in value.
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
567 getRegClassFor(VA.getLocVT()));
568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
569
570 // Get the high bits for i32 struct elements.
571 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
573 DAG.getConstant(32, MVT::i32));
574
575 // The caller promoted the argument, so insert an Assert?ext SDNode so we
576 // won't promote the value again in this function.
577 switch (VA.getLocInfo()) {
578 case CCValAssign::SExt:
579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
580 DAG.getValueType(VA.getValVT()));
581 break;
582 case CCValAssign::ZExt:
583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
584 DAG.getValueType(VA.getValVT()));
585 break;
586 default:
587 break;
588 }
589
590 // Truncate the register down to the argument type.
591 if (VA.isExtInLoc())
592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
593
594 InVals.push_back(Arg);
595 continue;
596 }
597
598 // The registers are exhausted. This argument was passed on the stack.
599 assert(VA.isMemLoc());
600 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
601 // beginning of the arguments area at %fp+BIAS+128.
602 unsigned Offset = VA.getLocMemOffset() + ArgArea;
603 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
604 // Adjust offset for extended arguments, SPARC is big-endian.
605 // The caller will have written the full slot with extended bytes, but we
606 // prefer our own extending loads.
607 if (VA.isExtInLoc())
608 Offset += 8 - ValSize;
609 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
610 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
611 DAG.getFrameIndex(FI, getPointerTy()),
612 MachinePointerInfo::getFixedStack(FI),
613 false, false, false, 0));
614 }
615
616 if (!IsVarArg)
617 return Chain;
618
619 // This function takes variable arguments, some of which may have been passed
620 // in registers %i0-%i5. Variable floating point arguments are never passed
621 // in floating point registers. They go on %i0-%i5 or on the stack like
622 // integer arguments.
623 //
624 // The va_start intrinsic needs to know the offset to the first variable
625 // argument.
626 unsigned ArgOffset = CCInfo.getNextStackOffset();
627 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
628 // Skip the 128 bytes of register save area.
629 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
630 Subtarget->getStackPointerBias());
631
632 // Save the variable arguments that were passed in registers.
633 // The caller is required to reserve stack space for 6 arguments regardless
634 // of how many arguments were actually passed.
635 SmallVector<SDValue, 8> OutChains;
636 for (; ArgOffset < 6*8; ArgOffset += 8) {
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
639 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
640 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
641 DAG.getFrameIndex(FI, getPointerTy()),
642 MachinePointerInfo::getFixedStack(FI),
643 false, false, 0));
644 }
645
646 if (!OutChains.empty())
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
648
649 return Chain;
650 }
651
652 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const653 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
654 SmallVectorImpl<SDValue> &InVals) const {
655 if (Subtarget->is64Bit())
656 return LowerCall_64(CLI, InVals);
657 return LowerCall_32(CLI, InVals);
658 }
659
hasReturnsTwiceAttr(SelectionDAG & DAG,SDValue Callee,ImmutableCallSite * CS)660 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
661 ImmutableCallSite *CS) {
662 if (CS)
663 return CS->hasFnAttr(Attribute::ReturnsTwice);
664
665 const Function *CalleeFn = nullptr;
666 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
667 CalleeFn = dyn_cast<Function>(G->getGlobal());
668 } else if (ExternalSymbolSDNode *E =
669 dyn_cast<ExternalSymbolSDNode>(Callee)) {
670 const Function *Fn = DAG.getMachineFunction().getFunction();
671 const Module *M = Fn->getParent();
672 const char *CalleeName = E->getSymbol();
673 CalleeFn = M->getFunction(CalleeName);
674 }
675
676 if (!CalleeFn)
677 return false;
678 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
679 }
680
681 // Lower a call for the 32-bit ABI.
682 SDValue
LowerCall_32(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const683 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
684 SmallVectorImpl<SDValue> &InVals) const {
685 SelectionDAG &DAG = CLI.DAG;
686 SDLoc &dl = CLI.DL;
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
688 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
689 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
690 SDValue Chain = CLI.Chain;
691 SDValue Callee = CLI.Callee;
692 bool &isTailCall = CLI.IsTailCall;
693 CallingConv::ID CallConv = CLI.CallConv;
694 bool isVarArg = CLI.IsVarArg;
695
696 // Sparc target does not yet support tail call optimization.
697 isTailCall = false;
698
699 // Analyze operands of the call, assigning locations to each operand.
700 SmallVector<CCValAssign, 16> ArgLocs;
701 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
702 DAG.getTarget(), ArgLocs, *DAG.getContext());
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
704
705 // Get the size of the outgoing arguments stack space requirement.
706 unsigned ArgsSize = CCInfo.getNextStackOffset();
707
708 // Keep stack frames 8-byte aligned.
709 ArgsSize = (ArgsSize+7) & ~7;
710
711 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
712
713 // Create local copies for byval args.
714 SmallVector<SDValue, 8> ByValArgs;
715 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
716 ISD::ArgFlagsTy Flags = Outs[i].Flags;
717 if (!Flags.isByVal())
718 continue;
719
720 SDValue Arg = OutVals[i];
721 unsigned Size = Flags.getByValSize();
722 unsigned Align = Flags.getByValAlign();
723
724 int FI = MFI->CreateStackObject(Size, Align, false);
725 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
726 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
727
728 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
729 false, // isVolatile,
730 (Size <= 32), // AlwaysInline if size <= 32
731 MachinePointerInfo(), MachinePointerInfo());
732 ByValArgs.push_back(FIPtr);
733 }
734
735 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
736 dl);
737
738 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
739 SmallVector<SDValue, 8> MemOpChains;
740
741 const unsigned StackOffset = 92;
742 bool hasStructRetAttr = false;
743 // Walk the register/memloc assignments, inserting copies/loads.
744 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
745 i != e;
746 ++i, ++realArgIdx) {
747 CCValAssign &VA = ArgLocs[i];
748 SDValue Arg = OutVals[realArgIdx];
749
750 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
751
752 // Use local copy if it is a byval arg.
753 if (Flags.isByVal())
754 Arg = ByValArgs[byvalArgIdx++];
755
756 // Promote the value if needed.
757 switch (VA.getLocInfo()) {
758 default: llvm_unreachable("Unknown loc info!");
759 case CCValAssign::Full: break;
760 case CCValAssign::SExt:
761 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
762 break;
763 case CCValAssign::ZExt:
764 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
765 break;
766 case CCValAssign::AExt:
767 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
768 break;
769 case CCValAssign::BCvt:
770 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
771 break;
772 }
773
774 if (Flags.isSRet()) {
775 assert(VA.needsCustom());
776 // store SRet argument in %sp+64
777 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
778 SDValue PtrOff = DAG.getIntPtrConstant(64);
779 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
780 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
781 MachinePointerInfo(),
782 false, false, 0));
783 hasStructRetAttr = true;
784 continue;
785 }
786
787 if (VA.needsCustom()) {
788 assert(VA.getLocVT() == MVT::f64);
789
790 if (VA.isMemLoc()) {
791 unsigned Offset = VA.getLocMemOffset() + StackOffset;
792 // if it is double-word aligned, just store.
793 if (Offset % 8 == 0) {
794 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
795 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
796 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
797 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
798 MachinePointerInfo(),
799 false, false, 0));
800 continue;
801 }
802 }
803
804 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
805 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
806 Arg, StackPtr, MachinePointerInfo(),
807 false, false, 0);
808 // Sparc is big-endian, so the high part comes first.
809 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
810 MachinePointerInfo(), false, false, false, 0);
811 // Increment the pointer to the other half.
812 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
813 DAG.getIntPtrConstant(4));
814 // Load the low part.
815 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
816 MachinePointerInfo(), false, false, false, 0);
817
818 if (VA.isRegLoc()) {
819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
820 assert(i+1 != e);
821 CCValAssign &NextVA = ArgLocs[++i];
822 if (NextVA.isRegLoc()) {
823 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
824 } else {
825 // Store the low part in stack.
826 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
827 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
828 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
829 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
830 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
831 MachinePointerInfo(),
832 false, false, 0));
833 }
834 } else {
835 unsigned Offset = VA.getLocMemOffset() + StackOffset;
836 // Store the high part.
837 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
838 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
839 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
840 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
841 MachinePointerInfo(),
842 false, false, 0));
843 // Store the low part.
844 PtrOff = DAG.getIntPtrConstant(Offset+4);
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
846 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
847 MachinePointerInfo(),
848 false, false, 0));
849 }
850 continue;
851 }
852
853 // Arguments that can be passed on register must be kept at
854 // RegsToPass vector
855 if (VA.isRegLoc()) {
856 if (VA.getLocVT() != MVT::f32) {
857 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
858 continue;
859 }
860 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
861 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
862 continue;
863 }
864
865 assert(VA.isMemLoc());
866
867 // Create a store off the stack pointer for this argument.
868 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
869 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
870 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
871 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
872 MachinePointerInfo(),
873 false, false, 0));
874 }
875
876
877 // Emit all stores, make sure the occur before any copies into physregs.
878 if (!MemOpChains.empty())
879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
880
881 // Build a sequence of copy-to-reg nodes chained together with token
882 // chain and flag operands which copy the outgoing args into registers.
883 // The InFlag in necessary since all emitted instructions must be
884 // stuck together.
885 SDValue InFlag;
886 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
887 unsigned Reg = toCallerWindow(RegsToPass[i].first);
888 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
889 InFlag = Chain.getValue(1);
890 }
891
892 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
893 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
894
895 // If the callee is a GlobalAddress node (quite common, every direct call is)
896 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
897 // Likewise ExternalSymbol -> TargetExternalSymbol.
898 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
899 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
900 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
901 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
902 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
903 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
904
905 // Returns a chain & a flag for retval copy to use
906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
907 SmallVector<SDValue, 8> Ops;
908 Ops.push_back(Chain);
909 Ops.push_back(Callee);
910 if (hasStructRetAttr)
911 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
912 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
913 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
914 RegsToPass[i].second.getValueType()));
915
916 // Add a register mask operand representing the call-preserved registers.
917 const SparcRegisterInfo *TRI =
918 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
919 const uint32_t *Mask = ((hasReturnsTwice)
920 ? TRI->getRTCallPreservedMask(CallConv)
921 : TRI->getCallPreservedMask(CallConv));
922 assert(Mask && "Missing call preserved mask for calling convention");
923 Ops.push_back(DAG.getRegisterMask(Mask));
924
925 if (InFlag.getNode())
926 Ops.push_back(InFlag);
927
928 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
929 InFlag = Chain.getValue(1);
930
931 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
932 DAG.getIntPtrConstant(0, true), InFlag, dl);
933 InFlag = Chain.getValue(1);
934
935 // Assign locations to each value returned by this call.
936 SmallVector<CCValAssign, 16> RVLocs;
937 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
938 DAG.getTarget(), RVLocs, *DAG.getContext());
939
940 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
941
942 // Copy all of the result registers out of their specified physreg.
943 for (unsigned i = 0; i != RVLocs.size(); ++i) {
944 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
945 RVLocs[i].getValVT(), InFlag).getValue(1);
946 InFlag = Chain.getValue(2);
947 InVals.push_back(Chain.getValue(0));
948 }
949
950 return Chain;
951 }
952
953 // This functions returns true if CalleeName is a ABI function that returns
954 // a long double (fp128).
isFP128ABICall(const char * CalleeName)955 static bool isFP128ABICall(const char *CalleeName)
956 {
957 static const char *const ABICalls[] =
958 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
959 "_Q_sqrt", "_Q_neg",
960 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
961 "_Q_lltoq", "_Q_ulltoq",
962 nullptr
963 };
964 for (const char * const *I = ABICalls; *I != nullptr; ++I)
965 if (strcmp(CalleeName, *I) == 0)
966 return true;
967 return false;
968 }
969
970 unsigned
getSRetArgSize(SelectionDAG & DAG,SDValue Callee) const971 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
972 {
973 const Function *CalleeFn = nullptr;
974 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
975 CalleeFn = dyn_cast<Function>(G->getGlobal());
976 } else if (ExternalSymbolSDNode *E =
977 dyn_cast<ExternalSymbolSDNode>(Callee)) {
978 const Function *Fn = DAG.getMachineFunction().getFunction();
979 const Module *M = Fn->getParent();
980 const char *CalleeName = E->getSymbol();
981 CalleeFn = M->getFunction(CalleeName);
982 if (!CalleeFn && isFP128ABICall(CalleeName))
983 return 16; // Return sizeof(fp128)
984 }
985
986 if (!CalleeFn)
987 return 0;
988
989 assert(CalleeFn->hasStructRetAttr() &&
990 "Callee does not have the StructRet attribute.");
991
992 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
993 Type *ElementTy = Ty->getElementType();
994 return getDataLayout()->getTypeAllocSize(ElementTy);
995 }
996
997
998 // Fixup floating point arguments in the ... part of a varargs call.
999 //
1000 // The SPARC v9 ABI requires that floating point arguments are treated the same
1001 // as integers when calling a varargs function. This does not apply to the
1002 // fixed arguments that are part of the function's prototype.
1003 //
1004 // This function post-processes a CCValAssign array created by
1005 // AnalyzeCallOperands().
fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> & ArgLocs,ArrayRef<ISD::OutputArg> Outs)1006 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1007 ArrayRef<ISD::OutputArg> Outs) {
1008 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1009 const CCValAssign &VA = ArgLocs[i];
1010 MVT ValTy = VA.getLocVT();
1011 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1012 // varargs functions.
1013 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1014 continue;
1015 // The fixed arguments to a varargs function still go in FP registers.
1016 if (Outs[VA.getValNo()].IsFixed)
1017 continue;
1018
1019 // This floating point argument should be reassigned.
1020 CCValAssign NewVA;
1021
1022 // Determine the offset into the argument array.
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1024 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1025 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1026 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1027
1028 if (Offset < 6*8) {
1029 // This argument should go in %i0-%i5.
1030 unsigned IReg = SP::I0 + Offset/8;
1031 if (ValTy == MVT::f64)
1032 // Full register, just bitconvert into i64.
1033 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1034 IReg, MVT::i64, CCValAssign::BCvt);
1035 else {
1036 assert(ValTy == MVT::f128 && "Unexpected type!");
1037 // Full register, just bitconvert into i128 -- We will lower this into
1038 // two i64s in LowerCall_64.
1039 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1040 IReg, MVT::i128, CCValAssign::BCvt);
1041 }
1042 } else {
1043 // This needs to go to memory, we're out of integer registers.
1044 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1045 Offset, VA.getLocVT(), VA.getLocInfo());
1046 }
1047 ArgLocs[i] = NewVA;
1048 }
1049 }
1050
1051 // Lower a call for the 64-bit ABI.
1052 SDValue
LowerCall_64(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1053 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1054 SmallVectorImpl<SDValue> &InVals) const {
1055 SelectionDAG &DAG = CLI.DAG;
1056 SDLoc DL = CLI.DL;
1057 SDValue Chain = CLI.Chain;
1058
1059 // Sparc target does not yet support tail call optimization.
1060 CLI.IsTailCall = false;
1061
1062 // Analyze operands of the call, assigning locations to each operand.
1063 SmallVector<CCValAssign, 16> ArgLocs;
1064 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1065 DAG.getTarget(), ArgLocs, *DAG.getContext());
1066 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1067
1068 // Get the size of the outgoing arguments stack space requirement.
1069 // The stack offset computed by CC_Sparc64 includes all arguments.
1070 // Called functions expect 6 argument words to exist in the stack frame, used
1071 // or not.
1072 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1073
1074 // Keep stack frames 16-byte aligned.
1075 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1076
1077 // Varargs calls require special treatment.
1078 if (CLI.IsVarArg)
1079 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1080
1081 // Adjust the stack pointer to make room for the arguments.
1082 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1083 // with more than 6 arguments.
1084 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1085 DL);
1086
1087 // Collect the set of registers to pass to the function and their values.
1088 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1089 // instruction.
1090 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1091
1092 // Collect chains from all the memory opeations that copy arguments to the
1093 // stack. They must follow the stack pointer adjustment above and precede the
1094 // call instruction itself.
1095 SmallVector<SDValue, 8> MemOpChains;
1096
1097 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1098 const CCValAssign &VA = ArgLocs[i];
1099 SDValue Arg = CLI.OutVals[i];
1100
1101 // Promote the value if needed.
1102 switch (VA.getLocInfo()) {
1103 default:
1104 llvm_unreachable("Unknown location info!");
1105 case CCValAssign::Full:
1106 break;
1107 case CCValAssign::SExt:
1108 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1109 break;
1110 case CCValAssign::ZExt:
1111 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1112 break;
1113 case CCValAssign::AExt:
1114 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1115 break;
1116 case CCValAssign::BCvt:
1117 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1118 // SPARC does not support i128 natively. Lower it into two i64, see below.
1119 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1120 || VA.getLocVT() != MVT::i128)
1121 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1122 break;
1123 }
1124
1125 if (VA.isRegLoc()) {
1126 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1127 && VA.getLocVT() == MVT::i128) {
1128 // Store and reload into the interger register reg and reg+1.
1129 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1130 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1131 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1132 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
1133 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1134 HiPtrOff);
1135 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
1136 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1137 LoPtrOff);
1138
1139 // Store to %sp+BIAS+128+Offset
1140 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1141 MachinePointerInfo(),
1142 false, false, 0);
1143 // Load into Reg and Reg+1
1144 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1145 MachinePointerInfo(),
1146 false, false, false, 0);
1147 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1148 MachinePointerInfo(),
1149 false, false, false, 0);
1150 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1151 Hi64));
1152 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1153 Lo64));
1154 continue;
1155 }
1156
1157 // The custom bit on an i32 return value indicates that it should be
1158 // passed in the high bits of the register.
1159 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1160 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1161 DAG.getConstant(32, MVT::i32));
1162
1163 // The next value may go in the low bits of the same register.
1164 // Handle both at once.
1165 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1166 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1167 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1168 CLI.OutVals[i+1]);
1169 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1170 // Skip the next value, it's already done.
1171 ++i;
1172 }
1173 }
1174 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1175 continue;
1176 }
1177
1178 assert(VA.isMemLoc());
1179
1180 // Create a store off the stack pointer for this argument.
1181 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1182 // The argument area starts at %fp+BIAS+128 in the callee frame,
1183 // %sp+BIAS+128 in ours.
1184 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1185 Subtarget->getStackPointerBias() +
1186 128);
1187 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1188 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1189 MachinePointerInfo(),
1190 false, false, 0));
1191 }
1192
1193 // Emit all stores, make sure they occur before the call.
1194 if (!MemOpChains.empty())
1195 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1196
1197 // Build a sequence of CopyToReg nodes glued together with token chain and
1198 // glue operands which copy the outgoing args into registers. The InGlue is
1199 // necessary since all emitted instructions must be stuck together in order
1200 // to pass the live physical registers.
1201 SDValue InGlue;
1202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1203 Chain = DAG.getCopyToReg(Chain, DL,
1204 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1205 InGlue = Chain.getValue(1);
1206 }
1207
1208 // If the callee is a GlobalAddress node (quite common, every direct call is)
1209 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1210 // Likewise ExternalSymbol -> TargetExternalSymbol.
1211 SDValue Callee = CLI.Callee;
1212 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1213 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1214 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1215 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1216 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
1217 TF);
1218 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1219 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF);
1220
1221 // Build the operands for the call instruction itself.
1222 SmallVector<SDValue, 8> Ops;
1223 Ops.push_back(Chain);
1224 Ops.push_back(Callee);
1225 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1226 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1227 RegsToPass[i].second.getValueType()));
1228
1229 // Add a register mask operand representing the call-preserved registers.
1230 const SparcRegisterInfo *TRI =
1231 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo();
1232 const uint32_t *Mask = ((hasReturnsTwice)
1233 ? TRI->getRTCallPreservedMask(CLI.CallConv)
1234 : TRI->getCallPreservedMask(CLI.CallConv));
1235 assert(Mask && "Missing call preserved mask for calling convention");
1236 Ops.push_back(DAG.getRegisterMask(Mask));
1237
1238 // Make sure the CopyToReg nodes are glued to the call instruction which
1239 // consumes the registers.
1240 if (InGlue.getNode())
1241 Ops.push_back(InGlue);
1242
1243 // Now the call itself.
1244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1245 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1246 InGlue = Chain.getValue(1);
1247
1248 // Revert the stack pointer immediately after the call.
1249 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1250 DAG.getIntPtrConstant(0, true), InGlue, DL);
1251 InGlue = Chain.getValue(1);
1252
1253 // Now extract the return values. This is more or less the same as
1254 // LowerFormalArguments_64.
1255
1256 // Assign locations to each value returned by this call.
1257 SmallVector<CCValAssign, 16> RVLocs;
1258 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
1259 DAG.getTarget(), RVLocs, *DAG.getContext());
1260
1261 // Set inreg flag manually for codegen generated library calls that
1262 // return float.
1263 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1264 CLI.Ins[0].Flags.setInReg();
1265
1266 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1267
1268 // Copy all of the result registers out of their specified physreg.
1269 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1270 CCValAssign &VA = RVLocs[i];
1271 unsigned Reg = toCallerWindow(VA.getLocReg());
1272
1273 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1274 // reside in the same register in the high and low bits. Reuse the
1275 // CopyFromReg previous node to avoid duplicate copies.
1276 SDValue RV;
1277 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1278 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1279 RV = Chain.getValue(0);
1280
1281 // But usually we'll create a new CopyFromReg for a different register.
1282 if (!RV.getNode()) {
1283 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1284 Chain = RV.getValue(1);
1285 InGlue = Chain.getValue(2);
1286 }
1287
1288 // Get the high bits for i32 struct elements.
1289 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1290 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1291 DAG.getConstant(32, MVT::i32));
1292
1293 // The callee promoted the return value, so insert an Assert?ext SDNode so
1294 // we won't promote the value again in this function.
1295 switch (VA.getLocInfo()) {
1296 case CCValAssign::SExt:
1297 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1298 DAG.getValueType(VA.getValVT()));
1299 break;
1300 case CCValAssign::ZExt:
1301 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1302 DAG.getValueType(VA.getValVT()));
1303 break;
1304 default:
1305 break;
1306 }
1307
1308 // Truncate the register down to the return value type.
1309 if (VA.isExtInLoc())
1310 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1311
1312 InVals.push_back(RV);
1313 }
1314
1315 return Chain;
1316 }
1317
1318 //===----------------------------------------------------------------------===//
1319 // TargetLowering Implementation
1320 //===----------------------------------------------------------------------===//
1321
1322 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1323 /// condition.
IntCondCCodeToICC(ISD::CondCode CC)1324 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1325 switch (CC) {
1326 default: llvm_unreachable("Unknown integer condition code!");
1327 case ISD::SETEQ: return SPCC::ICC_E;
1328 case ISD::SETNE: return SPCC::ICC_NE;
1329 case ISD::SETLT: return SPCC::ICC_L;
1330 case ISD::SETGT: return SPCC::ICC_G;
1331 case ISD::SETLE: return SPCC::ICC_LE;
1332 case ISD::SETGE: return SPCC::ICC_GE;
1333 case ISD::SETULT: return SPCC::ICC_CS;
1334 case ISD::SETULE: return SPCC::ICC_LEU;
1335 case ISD::SETUGT: return SPCC::ICC_GU;
1336 case ISD::SETUGE: return SPCC::ICC_CC;
1337 }
1338 }
1339
1340 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1341 /// FCC condition.
FPCondCCodeToFCC(ISD::CondCode CC)1342 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1343 switch (CC) {
1344 default: llvm_unreachable("Unknown fp condition code!");
1345 case ISD::SETEQ:
1346 case ISD::SETOEQ: return SPCC::FCC_E;
1347 case ISD::SETNE:
1348 case ISD::SETUNE: return SPCC::FCC_NE;
1349 case ISD::SETLT:
1350 case ISD::SETOLT: return SPCC::FCC_L;
1351 case ISD::SETGT:
1352 case ISD::SETOGT: return SPCC::FCC_G;
1353 case ISD::SETLE:
1354 case ISD::SETOLE: return SPCC::FCC_LE;
1355 case ISD::SETGE:
1356 case ISD::SETOGE: return SPCC::FCC_GE;
1357 case ISD::SETULT: return SPCC::FCC_UL;
1358 case ISD::SETULE: return SPCC::FCC_ULE;
1359 case ISD::SETUGT: return SPCC::FCC_UG;
1360 case ISD::SETUGE: return SPCC::FCC_UGE;
1361 case ISD::SETUO: return SPCC::FCC_U;
1362 case ISD::SETO: return SPCC::FCC_O;
1363 case ISD::SETONE: return SPCC::FCC_LG;
1364 case ISD::SETUEQ: return SPCC::FCC_UE;
1365 }
1366 }
1367
SparcTargetLowering(TargetMachine & TM)1368 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
1369 : TargetLowering(TM, new SparcELFTargetObjectFile()) {
1370 Subtarget = &TM.getSubtarget<SparcSubtarget>();
1371
1372 // Set up the register classes.
1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1377 if (Subtarget->is64Bit())
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1379
1380 // Turn FP extload into load/fextend
1381 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1382 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
1383
1384 // Sparc doesn't have i1 sign extending load
1385 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
1386
1387 // Turn FP truncstore into trunc + store.
1388 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1389 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1390 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1391
1392 // Custom legalize GlobalAddress nodes into LO/HI parts.
1393 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1394 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1395 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1396 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1397
1398 // Sparc doesn't have sext_inreg, replace them with shl/sra
1399 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1400 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1401 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1402
1403 // Sparc has no REM or DIVREM operations.
1404 setOperationAction(ISD::UREM, MVT::i32, Expand);
1405 setOperationAction(ISD::SREM, MVT::i32, Expand);
1406 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1407 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1408
1409 // ... nor does SparcV9.
1410 if (Subtarget->is64Bit()) {
1411 setOperationAction(ISD::UREM, MVT::i64, Expand);
1412 setOperationAction(ISD::SREM, MVT::i64, Expand);
1413 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1414 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1415 }
1416
1417 // Custom expand fp<->sint
1418 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1420 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1421 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1422
1423 // Custom Expand fp<->uint
1424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1427 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1428
1429 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1430 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1431
1432 // Sparc has no select or setcc: expand to SELECT_CC.
1433 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1434 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1435 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1436 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1437
1438 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1439 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1440 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1441 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1442
1443 // Sparc doesn't have BRCOND either, it has BR_CC.
1444 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1445 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1446 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1447 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1448 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1449 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1450 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1451
1452 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1453 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1454 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1455 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1456
1457 if (Subtarget->is64Bit()) {
1458 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1459 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1460 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1461 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1462 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1463 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1464 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1465 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1466 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1467 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1468
1469 setOperationAction(ISD::CTPOP, MVT::i64,
1470 Subtarget->usePopc() ? Legal : Expand);
1471 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1473 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1474 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1475 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1476 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1477 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1478 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1479 }
1480
1481 // ATOMICs.
1482 // FIXME: We insert fences for each atomics and generate sub-optimal code
1483 // for PSO/TSO. Also, implement other atomicrmw operations.
1484
1485 setInsertFencesForAtomic(true);
1486
1487 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1488 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1489 (Subtarget->isV9() ? Legal: Expand));
1490
1491
1492 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1493
1494 // Custom Lower Atomic LOAD/STORE
1495 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1496 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1497
1498 if (Subtarget->is64Bit()) {
1499 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1500 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1502 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1503 }
1504
1505 if (!Subtarget->isV9()) {
1506 // SparcV8 does not have FNEGD and FABSD.
1507 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1508 setOperationAction(ISD::FABS, MVT::f64, Custom);
1509 }
1510
1511 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1512 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1513 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1514 setOperationAction(ISD::FREM , MVT::f128, Expand);
1515 setOperationAction(ISD::FMA , MVT::f128, Expand);
1516 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1517 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1518 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1519 setOperationAction(ISD::FREM , MVT::f64, Expand);
1520 setOperationAction(ISD::FMA , MVT::f64, Expand);
1521 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1522 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1523 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1524 setOperationAction(ISD::FREM , MVT::f32, Expand);
1525 setOperationAction(ISD::FMA , MVT::f32, Expand);
1526 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1527 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1528 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1530 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1531 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1532 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1533 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1536 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1537 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1538 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1539
1540 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1541 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1542 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1543
1544 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1545 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1546 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1547
1548 if (Subtarget->is64Bit()) {
1549 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1550 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1551 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1552 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1553
1554 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1555 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1556
1557 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1558 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1559 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1560 }
1561
1562 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1563 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1564 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1566
1567 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1568
1569 // Use the default implementation.
1570 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1571 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1572 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1573 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1574 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1575
1576 setExceptionPointerRegister(SP::I0);
1577 setExceptionSelectorRegister(SP::I1);
1578
1579 setStackPointerRegisterToSaveRestore(SP::O6);
1580
1581 setOperationAction(ISD::CTPOP, MVT::i32,
1582 Subtarget->usePopc() ? Legal : Expand);
1583
1584 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1585 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1586 setOperationAction(ISD::STORE, MVT::f128, Legal);
1587 } else {
1588 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1589 setOperationAction(ISD::STORE, MVT::f128, Custom);
1590 }
1591
1592 if (Subtarget->hasHardQuad()) {
1593 setOperationAction(ISD::FADD, MVT::f128, Legal);
1594 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1595 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1596 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1597 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1598 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1599 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1600 if (Subtarget->isV9()) {
1601 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1602 setOperationAction(ISD::FABS, MVT::f128, Legal);
1603 } else {
1604 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1605 setOperationAction(ISD::FABS, MVT::f128, Custom);
1606 }
1607
1608 if (!Subtarget->is64Bit()) {
1609 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1610 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1611 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1612 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1613 }
1614
1615 } else {
1616 // Custom legalize f128 operations.
1617
1618 setOperationAction(ISD::FADD, MVT::f128, Custom);
1619 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1620 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1621 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1622 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1623 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1624 setOperationAction(ISD::FABS, MVT::f128, Custom);
1625
1626 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1627 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1628 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1629
1630 // Setup Runtime library names.
1631 if (Subtarget->is64Bit()) {
1632 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1633 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1634 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1635 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1636 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1637 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1638 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1639 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1640 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1641 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1642 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1643 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1644 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1645 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1646 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1647 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1648 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1649 } else {
1650 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1651 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1652 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1653 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1654 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1655 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1656 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1657 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1658 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1659 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1660 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1661 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1662 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1663 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1664 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1665 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1666 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1667 }
1668 }
1669
1670 setMinFunctionAlignment(2);
1671
1672 computeRegisterProperties();
1673 }
1674
getTargetNodeName(unsigned Opcode) const1675 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1676 switch (Opcode) {
1677 default: return nullptr;
1678 case SPISD::CMPICC: return "SPISD::CMPICC";
1679 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1680 case SPISD::BRICC: return "SPISD::BRICC";
1681 case SPISD::BRXCC: return "SPISD::BRXCC";
1682 case SPISD::BRFCC: return "SPISD::BRFCC";
1683 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1684 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1685 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1686 case SPISD::Hi: return "SPISD::Hi";
1687 case SPISD::Lo: return "SPISD::Lo";
1688 case SPISD::FTOI: return "SPISD::FTOI";
1689 case SPISD::ITOF: return "SPISD::ITOF";
1690 case SPISD::FTOX: return "SPISD::FTOX";
1691 case SPISD::XTOF: return "SPISD::XTOF";
1692 case SPISD::CALL: return "SPISD::CALL";
1693 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1694 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1695 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1696 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1697 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1698 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1699 }
1700 }
1701
getSetCCResultType(LLVMContext &,EVT VT) const1702 EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1703 if (!VT.isVector())
1704 return MVT::i32;
1705 return VT.changeVectorElementTypeToInteger();
1706 }
1707
1708 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1709 /// be zero. Op is expected to be a target specific node. Used by DAG
1710 /// combiner.
computeKnownBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const1711 void SparcTargetLowering::computeKnownBitsForTargetNode
1712 (const SDValue Op,
1713 APInt &KnownZero,
1714 APInt &KnownOne,
1715 const SelectionDAG &DAG,
1716 unsigned Depth) const {
1717 APInt KnownZero2, KnownOne2;
1718 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1719
1720 switch (Op.getOpcode()) {
1721 default: break;
1722 case SPISD::SELECT_ICC:
1723 case SPISD::SELECT_XCC:
1724 case SPISD::SELECT_FCC:
1725 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1726 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1727
1728 // Only known if known in both the LHS and RHS.
1729 KnownOne &= KnownOne2;
1730 KnownZero &= KnownZero2;
1731 break;
1732 }
1733 }
1734
1735 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1736 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
LookThroughSetCC(SDValue & LHS,SDValue & RHS,ISD::CondCode CC,unsigned & SPCC)1737 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1738 ISD::CondCode CC, unsigned &SPCC) {
1739 if (isa<ConstantSDNode>(RHS) &&
1740 cast<ConstantSDNode>(RHS)->isNullValue() &&
1741 CC == ISD::SETNE &&
1742 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1743 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1744 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1745 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1746 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1747 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1748 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1749 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1750 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1751 SDValue CMPCC = LHS.getOperand(3);
1752 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1753 LHS = CMPCC.getOperand(0);
1754 RHS = CMPCC.getOperand(1);
1755 }
1756 }
1757
1758 // Convert to a target node and set target flags.
withTargetFlags(SDValue Op,unsigned TF,SelectionDAG & DAG) const1759 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1760 SelectionDAG &DAG) const {
1761 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1762 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1763 SDLoc(GA),
1764 GA->getValueType(0),
1765 GA->getOffset(), TF);
1766
1767 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1768 return DAG.getTargetConstantPool(CP->getConstVal(),
1769 CP->getValueType(0),
1770 CP->getAlignment(),
1771 CP->getOffset(), TF);
1772
1773 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1774 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1775 Op.getValueType(),
1776 0,
1777 TF);
1778
1779 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1780 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1781 ES->getValueType(0), TF);
1782
1783 llvm_unreachable("Unhandled address SDNode");
1784 }
1785
1786 // Split Op into high and low parts according to HiTF and LoTF.
1787 // Return an ADD node combining the parts.
makeHiLoPair(SDValue Op,unsigned HiTF,unsigned LoTF,SelectionDAG & DAG) const1788 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1789 unsigned HiTF, unsigned LoTF,
1790 SelectionDAG &DAG) const {
1791 SDLoc DL(Op);
1792 EVT VT = Op.getValueType();
1793 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1794 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1795 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1796 }
1797
1798 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1799 // or ExternalSymbol SDNode.
makeAddress(SDValue Op,SelectionDAG & DAG) const1800 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1801 SDLoc DL(Op);
1802 EVT VT = getPointerTy();
1803
1804 // Handle PIC mode first.
1805 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1806 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1807 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1808 SparcMCExpr::VK_Sparc_GOT10, DAG);
1809 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1810 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1811 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1812 // function has calls.
1813 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1814 MFI->setHasCalls(true);
1815 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1816 MachinePointerInfo::getGOT(), false, false, false, 0);
1817 }
1818
1819 // This is one of the absolute code models.
1820 switch(getTargetMachine().getCodeModel()) {
1821 default:
1822 llvm_unreachable("Unsupported absolute code model");
1823 case CodeModel::Small:
1824 // abs32.
1825 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1826 SparcMCExpr::VK_Sparc_LO, DAG);
1827 case CodeModel::Medium: {
1828 // abs44.
1829 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1830 SparcMCExpr::VK_Sparc_M44, DAG);
1831 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1832 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1833 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1834 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1835 }
1836 case CodeModel::Large: {
1837 // abs64.
1838 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1839 SparcMCExpr::VK_Sparc_HM, DAG);
1840 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1841 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1842 SparcMCExpr::VK_Sparc_LO, DAG);
1843 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1844 }
1845 }
1846 }
1847
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1848 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1849 SelectionDAG &DAG) const {
1850 return makeAddress(Op, DAG);
1851 }
1852
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const1853 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1854 SelectionDAG &DAG) const {
1855 return makeAddress(Op, DAG);
1856 }
1857
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1858 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1859 SelectionDAG &DAG) const {
1860 return makeAddress(Op, DAG);
1861 }
1862
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1863 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1864 SelectionDAG &DAG) const {
1865
1866 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1867 SDLoc DL(GA);
1868 const GlobalValue *GV = GA->getGlobal();
1869 EVT PtrVT = getPointerTy();
1870
1871 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1872
1873 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1874 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1875 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1876 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1877 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1878 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1879 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1880 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1881 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1882 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1883 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1884 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1885 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1886
1887 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1888 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1889 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1890 withTargetFlags(Op, addTF, DAG));
1891
1892 SDValue Chain = DAG.getEntryNode();
1893 SDValue InFlag;
1894
1895 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1896 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1897 InFlag = Chain.getValue(1);
1898 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1899 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1900
1901 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1902 SmallVector<SDValue, 4> Ops;
1903 Ops.push_back(Chain);
1904 Ops.push_back(Callee);
1905 Ops.push_back(Symbol);
1906 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1907 const uint32_t *Mask = getTargetMachine()
1908 .getRegisterInfo()->getCallPreservedMask(CallingConv::C);
1909 assert(Mask && "Missing call preserved mask for calling convention");
1910 Ops.push_back(DAG.getRegisterMask(Mask));
1911 Ops.push_back(InFlag);
1912 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
1913 InFlag = Chain.getValue(1);
1914 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1915 DAG.getIntPtrConstant(0, true), InFlag, DL);
1916 InFlag = Chain.getValue(1);
1917 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1918
1919 if (model != TLSModel::LocalDynamic)
1920 return Ret;
1921
1922 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1923 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
1924 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1925 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
1926 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1927 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1928 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
1929 }
1930
1931 if (model == TLSModel::InitialExec) {
1932 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1933 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
1934
1935 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1936
1937 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1938 // function has calls.
1939 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1940 MFI->setHasCalls(true);
1941
1942 SDValue TGA = makeHiLoPair(Op,
1943 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
1944 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
1945 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1946 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1947 DL, PtrVT, Ptr,
1948 withTargetFlags(Op, ldTF, DAG));
1949 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1950 DAG.getRegister(SP::G7, PtrVT), Offset,
1951 withTargetFlags(Op,
1952 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
1953 }
1954
1955 assert(model == TLSModel::LocalExec);
1956 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1957 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
1958 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1959 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
1960 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1961
1962 return DAG.getNode(ISD::ADD, DL, PtrVT,
1963 DAG.getRegister(SP::G7, PtrVT), Offset);
1964 }
1965
1966 SDValue
LowerF128_LibCallArg(SDValue Chain,ArgListTy & Args,SDValue Arg,SDLoc DL,SelectionDAG & DAG) const1967 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1968 SDValue Arg, SDLoc DL,
1969 SelectionDAG &DAG) const {
1970 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1971 EVT ArgVT = Arg.getValueType();
1972 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1973
1974 ArgListEntry Entry;
1975 Entry.Node = Arg;
1976 Entry.Ty = ArgTy;
1977
1978 if (ArgTy->isFP128Ty()) {
1979 // Create a stack object and pass the pointer to the library function.
1980 int FI = MFI->CreateStackObject(16, 8, false);
1981 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1982 Chain = DAG.getStore(Chain,
1983 DL,
1984 Entry.Node,
1985 FIPtr,
1986 MachinePointerInfo(),
1987 false,
1988 false,
1989 8);
1990
1991 Entry.Node = FIPtr;
1992 Entry.Ty = PointerType::getUnqual(ArgTy);
1993 }
1994 Args.push_back(Entry);
1995 return Chain;
1996 }
1997
1998 SDValue
LowerF128Op(SDValue Op,SelectionDAG & DAG,const char * LibFuncName,unsigned numArgs) const1999 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2000 const char *LibFuncName,
2001 unsigned numArgs) const {
2002
2003 ArgListTy Args;
2004
2005 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2006
2007 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
2008 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2009 Type *RetTyABI = RetTy;
2010 SDValue Chain = DAG.getEntryNode();
2011 SDValue RetPtr;
2012
2013 if (RetTy->isFP128Ty()) {
2014 // Create a Stack Object to receive the return value of type f128.
2015 ArgListEntry Entry;
2016 int RetFI = MFI->CreateStackObject(16, 8, false);
2017 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
2018 Entry.Node = RetPtr;
2019 Entry.Ty = PointerType::getUnqual(RetTy);
2020 if (!Subtarget->is64Bit())
2021 Entry.isSRet = true;
2022 Entry.isReturned = false;
2023 Args.push_back(Entry);
2024 RetTyABI = Type::getVoidTy(*DAG.getContext());
2025 }
2026
2027 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2028 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2029 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2030 }
2031 TargetLowering::CallLoweringInfo CLI(DAG);
2032 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2033 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2034
2035 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2036
2037 // chain is in second result.
2038 if (RetTyABI == RetTy)
2039 return CallInfo.first;
2040
2041 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2042
2043 Chain = CallInfo.second;
2044
2045 // Load RetPtr to get the return value.
2046 return DAG.getLoad(Op.getValueType(),
2047 SDLoc(Op),
2048 Chain,
2049 RetPtr,
2050 MachinePointerInfo(),
2051 false, false, false, 8);
2052 }
2053
2054 SDValue
LowerF128Compare(SDValue LHS,SDValue RHS,unsigned & SPCC,SDLoc DL,SelectionDAG & DAG) const2055 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2056 unsigned &SPCC,
2057 SDLoc DL,
2058 SelectionDAG &DAG) const {
2059
2060 const char *LibCall = nullptr;
2061 bool is64Bit = Subtarget->is64Bit();
2062 switch(SPCC) {
2063 default: llvm_unreachable("Unhandled conditional code!");
2064 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2065 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2066 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2067 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2068 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2069 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2070 case SPCC::FCC_UL :
2071 case SPCC::FCC_ULE:
2072 case SPCC::FCC_UG :
2073 case SPCC::FCC_UGE:
2074 case SPCC::FCC_U :
2075 case SPCC::FCC_O :
2076 case SPCC::FCC_LG :
2077 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2078 }
2079
2080 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
2081 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2082 ArgListTy Args;
2083 SDValue Chain = DAG.getEntryNode();
2084 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2085 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2086
2087 TargetLowering::CallLoweringInfo CLI(DAG);
2088 CLI.setDebugLoc(DL).setChain(Chain)
2089 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2090
2091 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2092
2093 // result is in first, and chain is in second result.
2094 SDValue Result = CallInfo.first;
2095
2096 switch(SPCC) {
2097 default: {
2098 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2099 SPCC = SPCC::ICC_NE;
2100 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2101 }
2102 case SPCC::FCC_UL : {
2103 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
2104 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2105 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2106 SPCC = SPCC::ICC_NE;
2107 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2108 }
2109 case SPCC::FCC_ULE: {
2110 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
2111 SPCC = SPCC::ICC_NE;
2112 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2113 }
2114 case SPCC::FCC_UG : {
2115 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2116 SPCC = SPCC::ICC_G;
2117 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2118 }
2119 case SPCC::FCC_UGE: {
2120 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2121 SPCC = SPCC::ICC_NE;
2122 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2123 }
2124
2125 case SPCC::FCC_U : {
2126 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2127 SPCC = SPCC::ICC_E;
2128 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2129 }
2130 case SPCC::FCC_O : {
2131 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2132 SPCC = SPCC::ICC_NE;
2133 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2134 }
2135 case SPCC::FCC_LG : {
2136 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2137 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2138 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2139 SPCC = SPCC::ICC_NE;
2140 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2141 }
2142 case SPCC::FCC_UE : {
2143 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2144 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2145 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2146 SPCC = SPCC::ICC_E;
2147 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2148 }
2149 }
2150 }
2151
2152 static SDValue
LowerF128_FPEXTEND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2153 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2154 const SparcTargetLowering &TLI) {
2155
2156 if (Op.getOperand(0).getValueType() == MVT::f64)
2157 return TLI.LowerF128Op(Op, DAG,
2158 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2159
2160 if (Op.getOperand(0).getValueType() == MVT::f32)
2161 return TLI.LowerF128Op(Op, DAG,
2162 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2163
2164 llvm_unreachable("fpextend with non-float operand!");
2165 return SDValue();
2166 }
2167
2168 static SDValue
LowerF128_FPROUND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2169 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2170 const SparcTargetLowering &TLI) {
2171 // FP_ROUND on f64 and f32 are legal.
2172 if (Op.getOperand(0).getValueType() != MVT::f128)
2173 return Op;
2174
2175 if (Op.getValueType() == MVT::f64)
2176 return TLI.LowerF128Op(Op, DAG,
2177 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2178 if (Op.getValueType() == MVT::f32)
2179 return TLI.LowerF128Op(Op, DAG,
2180 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2181
2182 llvm_unreachable("fpround to non-float!");
2183 return SDValue();
2184 }
2185
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2186 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2187 const SparcTargetLowering &TLI,
2188 bool hasHardQuad) {
2189 SDLoc dl(Op);
2190 EVT VT = Op.getValueType();
2191 assert(VT == MVT::i32 || VT == MVT::i64);
2192
2193 // Expand f128 operations to fp128 abi calls.
2194 if (Op.getOperand(0).getValueType() == MVT::f128
2195 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2196 const char *libName = TLI.getLibcallName(VT == MVT::i32
2197 ? RTLIB::FPTOSINT_F128_I32
2198 : RTLIB::FPTOSINT_F128_I64);
2199 return TLI.LowerF128Op(Op, DAG, libName, 1);
2200 }
2201
2202 // Expand if the resulting type is illegal.
2203 if (!TLI.isTypeLegal(VT))
2204 return SDValue();
2205
2206 // Otherwise, Convert the fp value to integer in an FP register.
2207 if (VT == MVT::i32)
2208 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2209 else
2210 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2211
2212 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2213 }
2214
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2215 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2216 const SparcTargetLowering &TLI,
2217 bool hasHardQuad) {
2218 SDLoc dl(Op);
2219 EVT OpVT = Op.getOperand(0).getValueType();
2220 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2221
2222 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2223
2224 // Expand f128 operations to fp128 ABI calls.
2225 if (Op.getValueType() == MVT::f128
2226 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2227 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2228 ? RTLIB::SINTTOFP_I32_F128
2229 : RTLIB::SINTTOFP_I64_F128);
2230 return TLI.LowerF128Op(Op, DAG, libName, 1);
2231 }
2232
2233 // Expand if the operand type is illegal.
2234 if (!TLI.isTypeLegal(OpVT))
2235 return SDValue();
2236
2237 // Otherwise, Convert the int value to FP in an FP register.
2238 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2239 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2240 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2241 }
2242
LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2243 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2244 const SparcTargetLowering &TLI,
2245 bool hasHardQuad) {
2246 SDLoc dl(Op);
2247 EVT VT = Op.getValueType();
2248
2249 // Expand if it does not involve f128 or the target has support for
2250 // quad floating point instructions and the resulting type is legal.
2251 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2252 (hasHardQuad && TLI.isTypeLegal(VT)))
2253 return SDValue();
2254
2255 assert(VT == MVT::i32 || VT == MVT::i64);
2256
2257 return TLI.LowerF128Op(Op, DAG,
2258 TLI.getLibcallName(VT == MVT::i32
2259 ? RTLIB::FPTOUINT_F128_I32
2260 : RTLIB::FPTOUINT_F128_I64),
2261 1);
2262 }
2263
LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2264 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2265 const SparcTargetLowering &TLI,
2266 bool hasHardQuad) {
2267 SDLoc dl(Op);
2268 EVT OpVT = Op.getOperand(0).getValueType();
2269 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2270
2271 // Expand if it does not involve f128 or the target has support for
2272 // quad floating point instructions and the operand type is legal.
2273 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2274 return SDValue();
2275
2276 return TLI.LowerF128Op(Op, DAG,
2277 TLI.getLibcallName(OpVT == MVT::i32
2278 ? RTLIB::UINTTOFP_I32_F128
2279 : RTLIB::UINTTOFP_I64_F128),
2280 1);
2281 }
2282
LowerBR_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2283 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2284 const SparcTargetLowering &TLI,
2285 bool hasHardQuad) {
2286 SDValue Chain = Op.getOperand(0);
2287 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2288 SDValue LHS = Op.getOperand(2);
2289 SDValue RHS = Op.getOperand(3);
2290 SDValue Dest = Op.getOperand(4);
2291 SDLoc dl(Op);
2292 unsigned Opc, SPCC = ~0U;
2293
2294 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2295 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2296 LookThroughSetCC(LHS, RHS, CC, SPCC);
2297
2298 // Get the condition flag.
2299 SDValue CompareFlag;
2300 if (LHS.getValueType().isInteger()) {
2301 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2302 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2303 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2304 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2305 } else {
2306 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2307 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2308 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2309 Opc = SPISD::BRICC;
2310 } else {
2311 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2312 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2313 Opc = SPISD::BRFCC;
2314 }
2315 }
2316 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2317 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2318 }
2319
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2320 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2321 const SparcTargetLowering &TLI,
2322 bool hasHardQuad) {
2323 SDValue LHS = Op.getOperand(0);
2324 SDValue RHS = Op.getOperand(1);
2325 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2326 SDValue TrueVal = Op.getOperand(2);
2327 SDValue FalseVal = Op.getOperand(3);
2328 SDLoc dl(Op);
2329 unsigned Opc, SPCC = ~0U;
2330
2331 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2332 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2333 LookThroughSetCC(LHS, RHS, CC, SPCC);
2334
2335 SDValue CompareFlag;
2336 if (LHS.getValueType().isInteger()) {
2337 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2338 Opc = LHS.getValueType() == MVT::i32 ?
2339 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2340 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2341 } else {
2342 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2343 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2344 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2345 Opc = SPISD::SELECT_ICC;
2346 } else {
2347 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2348 Opc = SPISD::SELECT_FCC;
2349 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2350 }
2351 }
2352 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2353 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2354 }
2355
LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2356 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2357 const SparcTargetLowering &TLI) {
2358 MachineFunction &MF = DAG.getMachineFunction();
2359 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2360
2361 // Need frame address to find the address of VarArgsFrameIndex.
2362 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2363
2364 // vastart just stores the address of the VarArgsFrameIndex slot into the
2365 // memory location argument.
2366 SDLoc DL(Op);
2367 SDValue Offset =
2368 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2369 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2370 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2371 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2372 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2373 MachinePointerInfo(SV), false, false, 0);
2374 }
2375
LowerVAARG(SDValue Op,SelectionDAG & DAG)2376 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2377 SDNode *Node = Op.getNode();
2378 EVT VT = Node->getValueType(0);
2379 SDValue InChain = Node->getOperand(0);
2380 SDValue VAListPtr = Node->getOperand(1);
2381 EVT PtrVT = VAListPtr.getValueType();
2382 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2383 SDLoc DL(Node);
2384 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2385 MachinePointerInfo(SV), false, false, false, 0);
2386 // Increment the pointer, VAList, to the next vaarg.
2387 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2388 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2389 // Store the incremented VAList to the legalized pointer.
2390 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2391 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2392 // Load the actual argument out of the pointer VAList.
2393 // We can't count on greater alignment than the word size.
2394 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2395 false, false, false,
2396 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2397 }
2398
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2399 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2400 const SparcSubtarget *Subtarget) {
2401 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2402 SDValue Size = Op.getOperand(1); // Legalize the size.
2403 EVT VT = Size->getValueType(0);
2404 SDLoc dl(Op);
2405
2406 unsigned SPReg = SP::O6;
2407 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2408 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2409 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2410
2411 // The resultant pointer is actually 16 words from the bottom of the stack,
2412 // to provide a register spill area.
2413 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2414 regSpillArea += Subtarget->getStackPointerBias();
2415
2416 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2417 DAG.getConstant(regSpillArea, VT));
2418 SDValue Ops[2] = { NewVal, Chain };
2419 return DAG.getMergeValues(Ops, dl);
2420 }
2421
2422
getFLUSHW(SDValue Op,SelectionDAG & DAG)2423 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2424 SDLoc dl(Op);
2425 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2426 dl, MVT::Other, DAG.getEntryNode());
2427 return Chain;
2428 }
2429
getFRAMEADDR(uint64_t depth,SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2430 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2431 const SparcSubtarget *Subtarget) {
2432 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2433 MFI->setFrameAddressIsTaken(true);
2434
2435 EVT VT = Op.getValueType();
2436 SDLoc dl(Op);
2437 unsigned FrameReg = SP::I6;
2438 unsigned stackBias = Subtarget->getStackPointerBias();
2439
2440 SDValue FrameAddr;
2441
2442 if (depth == 0) {
2443 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2444 if (Subtarget->is64Bit())
2445 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2446 DAG.getIntPtrConstant(stackBias));
2447 return FrameAddr;
2448 }
2449
2450 // flush first to make sure the windowed registers' values are in stack
2451 SDValue Chain = getFLUSHW(Op, DAG);
2452 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2453
2454 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2455
2456 while (depth--) {
2457 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2458 DAG.getIntPtrConstant(Offset));
2459 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2460 false, false, false, 0);
2461 }
2462 if (Subtarget->is64Bit())
2463 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2464 DAG.getIntPtrConstant(stackBias));
2465 return FrameAddr;
2466 }
2467
2468
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2469 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2470 const SparcSubtarget *Subtarget) {
2471
2472 uint64_t depth = Op.getConstantOperandVal(0);
2473
2474 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2475
2476 }
2477
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,const SparcSubtarget * Subtarget)2478 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2479 const SparcTargetLowering &TLI,
2480 const SparcSubtarget *Subtarget) {
2481 MachineFunction &MF = DAG.getMachineFunction();
2482 MachineFrameInfo *MFI = MF.getFrameInfo();
2483 MFI->setReturnAddressIsTaken(true);
2484
2485 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2486 return SDValue();
2487
2488 EVT VT = Op.getValueType();
2489 SDLoc dl(Op);
2490 uint64_t depth = Op.getConstantOperandVal(0);
2491
2492 SDValue RetAddr;
2493 if (depth == 0) {
2494 unsigned RetReg = MF.addLiveIn(SP::I7,
2495 TLI.getRegClassFor(TLI.getPointerTy()));
2496 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2497 return RetAddr;
2498 }
2499
2500 // Need frame address to find return address of the caller.
2501 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2502
2503 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2504 SDValue Ptr = DAG.getNode(ISD::ADD,
2505 dl, VT,
2506 FrameAddr,
2507 DAG.getIntPtrConstant(Offset));
2508 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2509 MachinePointerInfo(), false, false, false, 0);
2510
2511 return RetAddr;
2512 }
2513
LowerF64Op(SDValue Op,SelectionDAG & DAG,unsigned opcode)2514 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2515 {
2516 SDLoc dl(Op);
2517
2518 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2519 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2520
2521 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2522 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2523 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2524
2525 SDValue SrcReg64 = Op.getOperand(0);
2526 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2527 SrcReg64);
2528 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2529 SrcReg64);
2530
2531 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2532
2533 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2534 dl, MVT::f64), 0);
2535 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2536 DstReg64, Hi32);
2537 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2538 DstReg64, Lo32);
2539 return DstReg64;
2540 }
2541
2542 // Lower a f128 load into two f64 loads.
LowerF128Load(SDValue Op,SelectionDAG & DAG)2543 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2544 {
2545 SDLoc dl(Op);
2546 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2547 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2548 && "Unexpected node type");
2549
2550 unsigned alignment = LdNode->getAlignment();
2551 if (alignment > 8)
2552 alignment = 8;
2553
2554 SDValue Hi64 = DAG.getLoad(MVT::f64,
2555 dl,
2556 LdNode->getChain(),
2557 LdNode->getBasePtr(),
2558 LdNode->getPointerInfo(),
2559 false, false, false, alignment);
2560 EVT addrVT = LdNode->getBasePtr().getValueType();
2561 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2562 LdNode->getBasePtr(),
2563 DAG.getConstant(8, addrVT));
2564 SDValue Lo64 = DAG.getLoad(MVT::f64,
2565 dl,
2566 LdNode->getChain(),
2567 LoPtr,
2568 LdNode->getPointerInfo(),
2569 false, false, false, alignment);
2570
2571 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2572 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2573
2574 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2575 dl, MVT::f128);
2576 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2577 MVT::f128,
2578 SDValue(InFP128, 0),
2579 Hi64,
2580 SubRegEven);
2581 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2582 MVT::f128,
2583 SDValue(InFP128, 0),
2584 Lo64,
2585 SubRegOdd);
2586 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2587 SDValue(Lo64.getNode(), 1) };
2588 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2589 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2590 return DAG.getMergeValues(Ops, dl);
2591 }
2592
2593 // Lower a f128 store into two f64 stores.
LowerF128Store(SDValue Op,SelectionDAG & DAG)2594 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2595 SDLoc dl(Op);
2596 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2597 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2598 && "Unexpected node type");
2599 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2600 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2601
2602 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2603 dl,
2604 MVT::f64,
2605 StNode->getValue(),
2606 SubRegEven);
2607 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2608 dl,
2609 MVT::f64,
2610 StNode->getValue(),
2611 SubRegOdd);
2612
2613 unsigned alignment = StNode->getAlignment();
2614 if (alignment > 8)
2615 alignment = 8;
2616
2617 SDValue OutChains[2];
2618 OutChains[0] = DAG.getStore(StNode->getChain(),
2619 dl,
2620 SDValue(Hi64, 0),
2621 StNode->getBasePtr(),
2622 MachinePointerInfo(),
2623 false, false, alignment);
2624 EVT addrVT = StNode->getBasePtr().getValueType();
2625 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2626 StNode->getBasePtr(),
2627 DAG.getConstant(8, addrVT));
2628 OutChains[1] = DAG.getStore(StNode->getChain(),
2629 dl,
2630 SDValue(Lo64, 0),
2631 LoPtr,
2632 MachinePointerInfo(),
2633 false, false, alignment);
2634 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2635 }
2636
LowerFNEGorFABS(SDValue Op,SelectionDAG & DAG,bool isV9)2637 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2638 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2639 && "invalid opcode");
2640
2641 if (Op.getValueType() == MVT::f64)
2642 return LowerF64Op(Op, DAG, Op.getOpcode());
2643 if (Op.getValueType() != MVT::f128)
2644 return Op;
2645
2646 // Lower fabs/fneg on f128 to fabs/fneg on f64
2647 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2648
2649 SDLoc dl(Op);
2650 SDValue SrcReg128 = Op.getOperand(0);
2651 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2652 SrcReg128);
2653 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2654 SrcReg128);
2655 if (isV9)
2656 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2657 else
2658 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2659
2660 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2661 dl, MVT::f128), 0);
2662 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2663 DstReg128, Hi64);
2664 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2665 DstReg128, Lo64);
2666 return DstReg128;
2667 }
2668
LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG)2669 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2670
2671 if (Op.getValueType() != MVT::i64)
2672 return Op;
2673
2674 SDLoc dl(Op);
2675 SDValue Src1 = Op.getOperand(0);
2676 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2677 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2678 DAG.getConstant(32, MVT::i64));
2679 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2680
2681 SDValue Src2 = Op.getOperand(1);
2682 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2683 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2684 DAG.getConstant(32, MVT::i64));
2685 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2686
2687
2688 bool hasChain = false;
2689 unsigned hiOpc = Op.getOpcode();
2690 switch (Op.getOpcode()) {
2691 default: llvm_unreachable("Invalid opcode");
2692 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2693 case ISD::ADDE: hasChain = true; break;
2694 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2695 case ISD::SUBE: hasChain = true; break;
2696 }
2697 SDValue Lo;
2698 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2699 if (hasChain) {
2700 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2701 Op.getOperand(2));
2702 } else {
2703 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2704 }
2705 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2706 SDValue Carry = Hi.getValue(1);
2707
2708 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2709 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2710 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2711 DAG.getConstant(32, MVT::i64));
2712
2713 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2714 SDValue Ops[2] = { Dst, Carry };
2715 return DAG.getMergeValues(Ops, dl);
2716 }
2717
2718 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2719 // in LegalizeDAG.cpp except the order of arguments to the library function.
LowerUMULO_SMULO(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2720 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2721 const SparcTargetLowering &TLI)
2722 {
2723 unsigned opcode = Op.getOpcode();
2724 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2725
2726 bool isSigned = (opcode == ISD::SMULO);
2727 EVT VT = MVT::i64;
2728 EVT WideVT = MVT::i128;
2729 SDLoc dl(Op);
2730 SDValue LHS = Op.getOperand(0);
2731
2732 if (LHS.getValueType() != VT)
2733 return Op;
2734
2735 SDValue ShiftAmt = DAG.getConstant(63, VT);
2736
2737 SDValue RHS = Op.getOperand(1);
2738 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2739 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2740 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2741
2742 SDValue MulResult = TLI.makeLibCall(DAG,
2743 RTLIB::MUL_I128, WideVT,
2744 Args, 4, isSigned, dl).first;
2745 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2746 MulResult, DAG.getIntPtrConstant(0));
2747 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2748 MulResult, DAG.getIntPtrConstant(1));
2749 if (isSigned) {
2750 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2751 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2752 } else {
2753 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
2754 ISD::SETNE);
2755 }
2756 // MulResult is a node with an illegal type. Because such things are not
2757 // generally permitted during this phase of legalization, delete the
2758 // node. The above EXTRACT_ELEMENT nodes should have been folded.
2759 DAG.DeleteNode(MulResult.getNode());
2760
2761 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2762 return DAG.getMergeValues(Ops, dl);
2763 }
2764
LowerATOMIC_LOAD_STORE(SDValue Op,SelectionDAG & DAG)2765 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2766 // Monotonic load/stores are legal.
2767 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2768 return Op;
2769
2770 // Otherwise, expand with a fence.
2771 return SDValue();
2772 }
2773
2774
2775 SDValue SparcTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const2776 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2777
2778 bool hasHardQuad = Subtarget->hasHardQuad();
2779 bool isV9 = Subtarget->isV9();
2780
2781 switch (Op.getOpcode()) {
2782 default: llvm_unreachable("Should not custom lower this!");
2783
2784 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2785 Subtarget);
2786 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2787 Subtarget);
2788 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2789 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2790 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2791 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2792 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2793 hasHardQuad);
2794 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2795 hasHardQuad);
2796 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2797 hasHardQuad);
2798 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2799 hasHardQuad);
2800 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2801 hasHardQuad);
2802 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2803 hasHardQuad);
2804 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2805 case ISD::VAARG: return LowerVAARG(Op, DAG);
2806 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2807 Subtarget);
2808
2809 case ISD::LOAD: return LowerF128Load(Op, DAG);
2810 case ISD::STORE: return LowerF128Store(Op, DAG);
2811 case ISD::FADD: return LowerF128Op(Op, DAG,
2812 getLibcallName(RTLIB::ADD_F128), 2);
2813 case ISD::FSUB: return LowerF128Op(Op, DAG,
2814 getLibcallName(RTLIB::SUB_F128), 2);
2815 case ISD::FMUL: return LowerF128Op(Op, DAG,
2816 getLibcallName(RTLIB::MUL_F128), 2);
2817 case ISD::FDIV: return LowerF128Op(Op, DAG,
2818 getLibcallName(RTLIB::DIV_F128), 2);
2819 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2820 getLibcallName(RTLIB::SQRT_F128),1);
2821 case ISD::FABS:
2822 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2823 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2824 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2825 case ISD::ADDC:
2826 case ISD::ADDE:
2827 case ISD::SUBC:
2828 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2829 case ISD::UMULO:
2830 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2831 case ISD::ATOMIC_LOAD:
2832 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2833 }
2834 }
2835
2836 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const2837 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2838 MachineBasicBlock *BB) const {
2839 switch (MI->getOpcode()) {
2840 default: llvm_unreachable("Unknown SELECT_CC!");
2841 case SP::SELECT_CC_Int_ICC:
2842 case SP::SELECT_CC_FP_ICC:
2843 case SP::SELECT_CC_DFP_ICC:
2844 case SP::SELECT_CC_QFP_ICC:
2845 return expandSelectCC(MI, BB, SP::BCOND);
2846 case SP::SELECT_CC_Int_FCC:
2847 case SP::SELECT_CC_FP_FCC:
2848 case SP::SELECT_CC_DFP_FCC:
2849 case SP::SELECT_CC_QFP_FCC:
2850 return expandSelectCC(MI, BB, SP::FBCOND);
2851
2852 case SP::ATOMIC_LOAD_ADD_32:
2853 return expandAtomicRMW(MI, BB, SP::ADDrr);
2854 case SP::ATOMIC_LOAD_ADD_64:
2855 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2856 case SP::ATOMIC_LOAD_SUB_32:
2857 return expandAtomicRMW(MI, BB, SP::SUBrr);
2858 case SP::ATOMIC_LOAD_SUB_64:
2859 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2860 case SP::ATOMIC_LOAD_AND_32:
2861 return expandAtomicRMW(MI, BB, SP::ANDrr);
2862 case SP::ATOMIC_LOAD_AND_64:
2863 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2864 case SP::ATOMIC_LOAD_OR_32:
2865 return expandAtomicRMW(MI, BB, SP::ORrr);
2866 case SP::ATOMIC_LOAD_OR_64:
2867 return expandAtomicRMW(MI, BB, SP::ORXrr);
2868 case SP::ATOMIC_LOAD_XOR_32:
2869 return expandAtomicRMW(MI, BB, SP::XORrr);
2870 case SP::ATOMIC_LOAD_XOR_64:
2871 return expandAtomicRMW(MI, BB, SP::XORXrr);
2872 case SP::ATOMIC_LOAD_NAND_32:
2873 return expandAtomicRMW(MI, BB, SP::ANDrr);
2874 case SP::ATOMIC_LOAD_NAND_64:
2875 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2876
2877 case SP::ATOMIC_SWAP_64:
2878 return expandAtomicRMW(MI, BB, 0);
2879
2880 case SP::ATOMIC_LOAD_MAX_32:
2881 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2882 case SP::ATOMIC_LOAD_MAX_64:
2883 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2884 case SP::ATOMIC_LOAD_MIN_32:
2885 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2886 case SP::ATOMIC_LOAD_MIN_64:
2887 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2888 case SP::ATOMIC_LOAD_UMAX_32:
2889 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2890 case SP::ATOMIC_LOAD_UMAX_64:
2891 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2892 case SP::ATOMIC_LOAD_UMIN_32:
2893 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2894 case SP::ATOMIC_LOAD_UMIN_64:
2895 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2896 }
2897 }
2898
2899 MachineBasicBlock*
expandSelectCC(MachineInstr * MI,MachineBasicBlock * BB,unsigned BROpcode) const2900 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2901 MachineBasicBlock *BB,
2902 unsigned BROpcode) const {
2903 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2904 DebugLoc dl = MI->getDebugLoc();
2905 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2906
2907 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2908 // control-flow pattern. The incoming instruction knows the destination vreg
2909 // to set, the condition code register to branch on, the true/false values to
2910 // select between, and a branch opcode to use.
2911 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2912 MachineFunction::iterator It = BB;
2913 ++It;
2914
2915 // thisMBB:
2916 // ...
2917 // TrueVal = ...
2918 // [f]bCC copy1MBB
2919 // fallthrough --> copy0MBB
2920 MachineBasicBlock *thisMBB = BB;
2921 MachineFunction *F = BB->getParent();
2922 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2923 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2924 F->insert(It, copy0MBB);
2925 F->insert(It, sinkMBB);
2926
2927 // Transfer the remainder of BB and its successor edges to sinkMBB.
2928 sinkMBB->splice(sinkMBB->begin(), BB,
2929 std::next(MachineBasicBlock::iterator(MI)),
2930 BB->end());
2931 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2932
2933 // Add the true and fallthrough blocks as its successors.
2934 BB->addSuccessor(copy0MBB);
2935 BB->addSuccessor(sinkMBB);
2936
2937 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2938
2939 // copy0MBB:
2940 // %FalseValue = ...
2941 // # fallthrough to sinkMBB
2942 BB = copy0MBB;
2943
2944 // Update machine-CFG edges
2945 BB->addSuccessor(sinkMBB);
2946
2947 // sinkMBB:
2948 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2949 // ...
2950 BB = sinkMBB;
2951 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2952 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2953 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2954
2955 MI->eraseFromParent(); // The pseudo instruction is gone now.
2956 return BB;
2957 }
2958
2959 MachineBasicBlock*
expandAtomicRMW(MachineInstr * MI,MachineBasicBlock * MBB,unsigned Opcode,unsigned CondCode) const2960 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2961 MachineBasicBlock *MBB,
2962 unsigned Opcode,
2963 unsigned CondCode) const {
2964 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
2965 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2966 DebugLoc DL = MI->getDebugLoc();
2967
2968 // MI is an atomic read-modify-write instruction of the form:
2969 //
2970 // rd = atomicrmw<op> addr, rs2
2971 //
2972 // All three operands are registers.
2973 unsigned DestReg = MI->getOperand(0).getReg();
2974 unsigned AddrReg = MI->getOperand(1).getReg();
2975 unsigned Rs2Reg = MI->getOperand(2).getReg();
2976
2977 // SelectionDAG has already inserted memory barriers before and after MI, so
2978 // we simply have to implement the operatiuon in terms of compare-and-swap.
2979 //
2980 // %val0 = load %addr
2981 // loop:
2982 // %val = phi %val0, %dest
2983 // %upd = op %val, %rs2
2984 // %dest = cas %addr, %val, %upd
2985 // cmp %val, %dest
2986 // bne loop
2987 // done:
2988 //
2989 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
2990 const TargetRegisterClass *ValueRC =
2991 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
2992 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
2993
2994 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
2995 .addReg(AddrReg).addImm(0);
2996
2997 // Split the basic block MBB before MI and insert the loop block in the hole.
2998 MachineFunction::iterator MFI = MBB;
2999 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3000 MachineFunction *MF = MBB->getParent();
3001 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3002 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3003 ++MFI;
3004 MF->insert(MFI, LoopMBB);
3005 MF->insert(MFI, DoneMBB);
3006
3007 // Move MI and following instructions to DoneMBB.
3008 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3009 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3010
3011 // Connect the CFG again.
3012 MBB->addSuccessor(LoopMBB);
3013 LoopMBB->addSuccessor(LoopMBB);
3014 LoopMBB->addSuccessor(DoneMBB);
3015
3016 // Build the loop block.
3017 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3018 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3019 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3020
3021 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3022 .addReg(Val0Reg).addMBB(MBB)
3023 .addReg(DestReg).addMBB(LoopMBB);
3024
3025 if (CondCode) {
3026 // This is one of the min/max operations. We need a CMPrr followed by a
3027 // MOVXCC/MOVICC.
3028 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3029 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3030 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3031 } else if (Opcode) {
3032 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3033 .addReg(ValReg).addReg(Rs2Reg);
3034 }
3035
3036 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3037 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3038 unsigned TmpReg = UpdReg;
3039 UpdReg = MRI.createVirtualRegister(ValueRC);
3040 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3041 }
3042
3043 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3044 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3045 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3046 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3047 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3048 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3049
3050 MI->eraseFromParent();
3051 return DoneMBB;
3052 }
3053
3054 //===----------------------------------------------------------------------===//
3055 // Sparc Inline Assembly Support
3056 //===----------------------------------------------------------------------===//
3057
3058 /// getConstraintType - Given a constraint letter, return the type of
3059 /// constraint it is for this target.
3060 SparcTargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const3061 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
3062 if (Constraint.size() == 1) {
3063 switch (Constraint[0]) {
3064 default: break;
3065 case 'r': return C_RegisterClass;
3066 case 'I': // SIMM13
3067 return C_Other;
3068 }
3069 }
3070
3071 return TargetLowering::getConstraintType(Constraint);
3072 }
3073
3074 TargetLowering::ConstraintWeight SparcTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3075 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3076 const char *constraint) const {
3077 ConstraintWeight weight = CW_Invalid;
3078 Value *CallOperandVal = info.CallOperandVal;
3079 // If we don't have a value, we can't do a match,
3080 // but allow it at the lowest weight.
3081 if (!CallOperandVal)
3082 return CW_Default;
3083
3084 // Look at the constraint type.
3085 switch (*constraint) {
3086 default:
3087 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3088 break;
3089 case 'I': // SIMM13
3090 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3091 if (isInt<13>(C->getSExtValue()))
3092 weight = CW_Constant;
3093 }
3094 break;
3095 }
3096 return weight;
3097 }
3098
3099 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3100 /// vector. If it is invalid, don't add anything to Ops.
3101 void SparcTargetLowering::
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3102 LowerAsmOperandForConstraint(SDValue Op,
3103 std::string &Constraint,
3104 std::vector<SDValue> &Ops,
3105 SelectionDAG &DAG) const {
3106 SDValue Result(nullptr, 0);
3107
3108 // Only support length 1 constraints for now.
3109 if (Constraint.length() > 1)
3110 return;
3111
3112 char ConstraintLetter = Constraint[0];
3113 switch (ConstraintLetter) {
3114 default: break;
3115 case 'I':
3116 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3117 if (isInt<13>(C->getSExtValue())) {
3118 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
3119 break;
3120 }
3121 return;
3122 }
3123 }
3124
3125 if (Result.getNode()) {
3126 Ops.push_back(Result);
3127 return;
3128 }
3129 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3130 }
3131
3132 std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string & Constraint,MVT VT) const3133 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3134 MVT VT) const {
3135 if (Constraint.size() == 1) {
3136 switch (Constraint[0]) {
3137 case 'r':
3138 return std::make_pair(0U, &SP::IntRegsRegClass);
3139 }
3140 } else if (!Constraint.empty() && Constraint.size() <= 5
3141 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3142 // constraint = '{r<d>}'
3143 // Remove the braces from around the name.
3144 StringRef name(Constraint.data()+1, Constraint.size()-2);
3145 // Handle register aliases:
3146 // r0-r7 -> g0-g7
3147 // r8-r15 -> o0-o7
3148 // r16-r23 -> l0-l7
3149 // r24-r31 -> i0-i7
3150 uint64_t intVal = 0;
3151 if (name.substr(0, 1).equals("r")
3152 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3153 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3154 char regType = regTypes[intVal/8];
3155 char regIdx = '0' + (intVal % 8);
3156 char tmp[] = { '{', regType, regIdx, '}', 0 };
3157 std::string newConstraint = std::string(tmp);
3158 return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
3159 }
3160 }
3161
3162 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3163 }
3164
3165 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3166 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3167 // The Sparc target isn't yet aware of offsets.
3168 return false;
3169 }
3170
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const3171 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3172 SmallVectorImpl<SDValue>& Results,
3173 SelectionDAG &DAG) const {
3174
3175 SDLoc dl(N);
3176
3177 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3178
3179 switch (N->getOpcode()) {
3180 default:
3181 llvm_unreachable("Do not know how to custom type legalize this operation!");
3182
3183 case ISD::FP_TO_SINT:
3184 case ISD::FP_TO_UINT:
3185 // Custom lower only if it involves f128 or i64.
3186 if (N->getOperand(0).getValueType() != MVT::f128
3187 || N->getValueType(0) != MVT::i64)
3188 return;
3189 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3190 ? RTLIB::FPTOSINT_F128_I64
3191 : RTLIB::FPTOUINT_F128_I64);
3192
3193 Results.push_back(LowerF128Op(SDValue(N, 0),
3194 DAG,
3195 getLibcallName(libCall),
3196 1));
3197 return;
3198
3199 case ISD::SINT_TO_FP:
3200 case ISD::UINT_TO_FP:
3201 // Custom lower only if it involves f128 or i64.
3202 if (N->getValueType(0) != MVT::f128
3203 || N->getOperand(0).getValueType() != MVT::i64)
3204 return;
3205
3206 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3207 ? RTLIB::SINTTOFP_I64_F128
3208 : RTLIB::UINTTOFP_I64_F128);
3209
3210 Results.push_back(LowerF128Op(SDValue(N, 0),
3211 DAG,
3212 getLibcallName(libCall),
3213 1));
3214 return;
3215 }
3216 }
3217