| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 61 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
109 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
215 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
452 unsigned PredReg; in rewriteT2FrameIndex() local
625 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getITInstrPredicate()
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| D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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| D | ARMLoadStoreOptimizer.cpp | 336 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses()
417 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps()
616 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate()
710 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR()
795 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingDecrement()
830 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingIncrement()
994 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1151 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1365 ARMCC::CondCodes Pred, unsigned PredReg, in InsertLDR_STR()
1415 unsigned PredReg = 0; in FixInvalidRegPairOp() local
[all …]
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| D | Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0; in ReduceSpecial() local
685 unsigned PredReg = 0; in ReduceTo2Addr() local
782 unsigned PredReg = 0; in ReduceToNarrow() local
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| D | Thumb1RegisterInfo.cpp | 67 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
371 unsigned PredReg; in rewriteFrameIndex() local
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| D | ARMBaseRegisterInfo.cpp | 403 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
760 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0; in InsertITInstructions() local
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| D | ARMFrameLowering.cpp | 120 unsigned PredReg = 0) { in emitRegPlusImmediate()
134 unsigned PredReg = 0) { in emitSPUpdate()
1658 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1663 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
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| D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| D | ARMISelDAGToDAG.cpp | 2468 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2731 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2751 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2770 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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| D | ARMConstantIslandPass.cpp | 1350 unsigned PredReg = 0; in createNewWater() local
1796 unsigned PredReg = 0; in optimizeThumb2Branches() local
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| D | ARMExpandPseudoInsts.cpp | 656 unsigned PredReg = 0; in ExpandMOV32BitImm() local
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| D | ARMBaseInstrInfo.cpp | 1634 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate()
1664 unsigned PredReg = 0; in commuteInstruction() local
1843 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 500 unsigned PredReg = Cond[Cond.size()-1].getReg(); in getLoopTripCount() local
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