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Searched defs:RC (Results 1 – 25 of 146) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm/include/llvm/IR/
DIRBuilder.h635 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
649 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
657 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
671 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
679 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
693 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
701 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
713 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
725 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
732 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h125 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
458 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
484 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
584 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
593 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
605 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
660 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { in avoidWriteAfterWrite()
[all …]
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp83 const TargetRegisterClass *RC; in getGlobalBaseReg() local
101 const TargetRegisterClass *RC; in getMips16SPAliasReg() local
109 const TargetRegisterClass *RC = ST.isABI_N64() ? in createEhDataRegsFI() local
DMipsSEFrameLowering.cpp134 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
177 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
207 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
357 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue() local
423 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitEpilogue() local
471 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
531 const TargetRegisterClass *RC = STI.hasMips64() ? in processFunctionBeforeCalleeSavedScan() local
545 const TargetRegisterClass *RC = STI.isABI_N64() ? in processFunctionBeforeCalleeSavedScan() local
DMipsInstrInfo.h93 const TargetRegisterClass *RC, in storeRegToStackSlot()
101 const TargetRegisterClass *RC, in loadRegFromStackSlot()
DMipsFastISel.cpp91 unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, in FastEmitInst_riir()
325 const TargetRegisterClass *RC = &Mips::FGR32RegClass; in MaterializeFP() local
331 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in MaterializeFP() local
346 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in MaterializeGV() local
360 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in MaterializeInt() local
371 const TargetRegisterClass *RC) { in Materialize32BitInt()
/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp143 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in inferRegClassFromUses() local
165 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef() local
224 const TargetRegisterClass *RC = inferRegClassFromDef(TRI, MRI, Reg, in runOnMachineFunction() local
229 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction() local
DSIRegisterInfo.cpp35 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
109 const TargetRegisterClass *RC, unsigned SubIdx) const { in getSubRegClass() argument
/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp59 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
81 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
DTargetRegisterInfo.cpp118 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
131 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
235 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
DAggressiveAntiDepBreaker.h45 const TargetRegisterClass *RC; member
DPrologEpilogInserter.cpp286 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); in calculateCalleeSavedRegisters() local
355 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
383 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores() local
883 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); in scavengeFrameVirtualRegs() local
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp428 const TargetRegisterClass *RC, in PPCEmitLoad()
557 const TargetRegisterClass *RC = in SelectLoad() local
573 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
908 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
969 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1013 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1101 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1262 const TargetRegisterClass *RC = in processCallArgs() local
1274 const TargetRegisterClass *RC = in processCallArgs() local
1585 const TargetRegisterClass *RC = in SelectRet() local
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp53 const TargetRegisterClass *RC, in storeRegToStackSlot()
81 const TargetRegisterClass *RC, in loadRegFromStackSlot()
DARMFastISel.cpp287 const TargetRegisterClass *RC, in FastEmitInst_r()
309 const TargetRegisterClass *RC, in FastEmitInst_rr()
337 const TargetRegisterClass *RC, in FastEmitInst_rrr()
369 const TargetRegisterClass *RC, in FastEmitInst_ri()
395 const TargetRegisterClass *RC, in FastEmitInst_rri()
425 const TargetRegisterClass *RC, in FastEmitInst_i()
521 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
581 const TargetRegisterClass *RC = isThumb2 ? in ARMMaterializeGV() local
715 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in TargetMaterializeAlloca() local
888 const TargetRegisterClass *RC = isThumb2 ? in ARMSimplifyAddress() local
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1322 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { in createResultReg()
1344 const TargetRegisterClass* RC) { in FastEmitInst_()
1353 const TargetRegisterClass *RC, in FastEmitInst_r()
1374 const TargetRegisterClass *RC, in FastEmitInst_rr()
1398 const TargetRegisterClass *RC, in FastEmitInst_rrr()
1426 const TargetRegisterClass *RC, in FastEmitInst_ri()
1450 const TargetRegisterClass *RC, in FastEmitInst_rii()
1475 const TargetRegisterClass *RC, in FastEmitInst_rf()
1498 const TargetRegisterClass *RC, in FastEmitInst_rri()
1525 const TargetRegisterClass *RC, in FastEmitInst_rrii()
[all …]
DResourcePriorityQueue.cpp371 const TargetRegisterClass *RC = *I; in regPressureDelta() local
378 const TargetRegisterClass *RC = *I; in regPressureDelta() local
491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; in EmitRegUnitPressure() local
853 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
887 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
995 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetHeader() local
1033 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1098 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1127 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
1143 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1179 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
1245 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; in runTargetDesc() local
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp40 const TargetRegisterClass *RC, in storeRegToStackSlot()
68 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp368 const TargetRegisterClass *RC = nullptr; in X86FastEmitLoad() local
594 const TargetRegisterClass *RC = nullptr; in handleConstantAddresses() local
1501 const TargetRegisterClass *RC = nullptr; in X86SelectShift() local
1585 const TargetRegisterClass *RC; in X86SelectDivRem() member
1744 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect() local
1922 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect() local
1991 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect() local
2019 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect() local
2193 const TargetRegisterClass *RC = nullptr; in X86VisitIntrinsicCall() local
2332 const TargetRegisterClass *RC; in X86VisitIntrinsicCall() local
[all …]
/external/clang/test/CodeGenCXX/
Ddevirtualize-virtual-function-calls-final.cpp169 struct RC final : public RA { struct
170 virtual C *f() { in f()
/external/clang/test/Layout/
Dms-x86-pack-and-align.cpp450 struct RC { struct
456 RC c; argument

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