1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef TCG_TARGET_I386
25 #define TCG_TARGET_I386 1
26
27 #undef TCG_TARGET_WORDS_BIGENDIAN
28
29 #ifdef __x86_64__
30 # define TCG_TARGET_REG_BITS 64
31 # define TCG_TARGET_NB_REGS 16
32 #else
33 # define TCG_TARGET_REG_BITS 32
34 # define TCG_TARGET_NB_REGS 8
35 #endif
36
37 typedef enum {
38 TCG_REG_EAX = 0,
39 TCG_REG_ECX,
40 TCG_REG_EDX,
41 TCG_REG_EBX,
42 TCG_REG_ESP,
43 TCG_REG_EBP,
44 TCG_REG_ESI,
45 TCG_REG_EDI,
46
47 /* 64-bit registers; always define the symbols to avoid
48 too much if-deffing. */
49 TCG_REG_R8,
50 TCG_REG_R9,
51 TCG_REG_R10,
52 TCG_REG_R11,
53 TCG_REG_R12,
54 TCG_REG_R13,
55 TCG_REG_R14,
56 TCG_REG_R15,
57 TCG_REG_RAX = TCG_REG_EAX,
58 TCG_REG_RCX = TCG_REG_ECX,
59 TCG_REG_RDX = TCG_REG_EDX,
60 TCG_REG_RBX = TCG_REG_EBX,
61 TCG_REG_RSP = TCG_REG_ESP,
62 TCG_REG_RBP = TCG_REG_EBP,
63 TCG_REG_RSI = TCG_REG_ESI,
64 TCG_REG_RDI = TCG_REG_EDI,
65 } TCGReg;
66
67 #define TCG_CT_CONST_S32 0x100
68 #define TCG_CT_CONST_U32 0x200
69
70 /* used for function call generation */
71 #define TCG_REG_CALL_STACK TCG_REG_ESP
72 #define TCG_TARGET_STACK_ALIGN 16
73 #if defined(_WIN64)
74 #define TCG_TARGET_CALL_STACK_OFFSET 32
75 #else
76 #define TCG_TARGET_CALL_STACK_OFFSET 0
77 #endif
78
79 /* optional instructions */
80 #define TCG_TARGET_HAS_div2_i32 1
81 #define TCG_TARGET_HAS_rot_i32 1
82 #define TCG_TARGET_HAS_ext8s_i32 1
83 #define TCG_TARGET_HAS_ext16s_i32 1
84 #define TCG_TARGET_HAS_ext8u_i32 1
85 #define TCG_TARGET_HAS_ext16u_i32 1
86 #define TCG_TARGET_HAS_bswap16_i32 1
87 #define TCG_TARGET_HAS_bswap32_i32 1
88 #define TCG_TARGET_HAS_neg_i32 1
89 #define TCG_TARGET_HAS_not_i32 1
90 #define TCG_TARGET_HAS_andc_i32 0
91 #define TCG_TARGET_HAS_orc_i32 0
92 #define TCG_TARGET_HAS_eqv_i32 0
93 #define TCG_TARGET_HAS_nand_i32 0
94 #define TCG_TARGET_HAS_nor_i32 0
95 #define TCG_TARGET_HAS_deposit_i32 1
96 #define TCG_TARGET_HAS_movcond_i32 1
97 #define TCG_TARGET_HAS_add2_i32 1
98 #define TCG_TARGET_HAS_sub2_i32 1
99 #define TCG_TARGET_HAS_mulu2_i32 1
100 #define TCG_TARGET_HAS_muls2_i32 1
101 #define TCG_TARGET_HAS_muluh_i32 0
102 #define TCG_TARGET_HAS_mulsh_i32 0
103
104 #if TCG_TARGET_REG_BITS == 64
105 #define TCG_TARGET_HAS_div2_i64 1
106 #define TCG_TARGET_HAS_rot_i64 1
107 #define TCG_TARGET_HAS_ext8s_i64 1
108 #define TCG_TARGET_HAS_ext16s_i64 1
109 #define TCG_TARGET_HAS_ext32s_i64 1
110 #define TCG_TARGET_HAS_ext8u_i64 1
111 #define TCG_TARGET_HAS_ext16u_i64 1
112 #define TCG_TARGET_HAS_ext32u_i64 1
113 #define TCG_TARGET_HAS_bswap16_i64 1
114 #define TCG_TARGET_HAS_bswap32_i64 1
115 #define TCG_TARGET_HAS_bswap64_i64 1
116 #define TCG_TARGET_HAS_neg_i64 1
117 #define TCG_TARGET_HAS_not_i64 1
118 #define TCG_TARGET_HAS_andc_i64 0
119 #define TCG_TARGET_HAS_orc_i64 0
120 #define TCG_TARGET_HAS_eqv_i64 0
121 #define TCG_TARGET_HAS_nand_i64 0
122 #define TCG_TARGET_HAS_nor_i64 0
123 #define TCG_TARGET_HAS_deposit_i64 1
124 #define TCG_TARGET_HAS_movcond_i64 1
125 #define TCG_TARGET_HAS_add2_i64 1
126 #define TCG_TARGET_HAS_sub2_i64 1
127 #define TCG_TARGET_HAS_mulu2_i64 1
128 #define TCG_TARGET_HAS_muls2_i64 1
129 #define TCG_TARGET_HAS_muluh_i64 0
130 #define TCG_TARGET_HAS_mulsh_i64 0
131 #endif
132
133 #define TCG_TARGET_HAS_new_ldst 1
134
135 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
136 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
137 ((ofs) == 0 && (len) == 16))
138 #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
139
140 #if TCG_TARGET_REG_BITS == 64
141 # define TCG_AREG0 TCG_REG_R14
142 #else
143 # define TCG_AREG0 TCG_REG_EBP
144 #endif
145
flush_icache_range(uintptr_t start,uintptr_t stop)146 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
147 {
148 }
149
150 #endif
151