| /external/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 75 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
89 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
102 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
120 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
133 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
141 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 73 unsigned VirtReg; // Virtual register number. member
181 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
202 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
257 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
267 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
403 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
419 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
446 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
467 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
500 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
[all …]
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| D | RegAllocGreedy.cpp | 201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
454 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
464 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
568 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
612 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
675 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
757 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
798 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1290 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1320 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
[all …]
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| D | VirtRegMap.cpp | 83 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
92 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
243 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
338 unsigned VirtReg = MO.getReg(); in rewrite() local
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| D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { in extract()
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| D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
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| D | RegAllocBasic.cpp | 167 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
221 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
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| D | RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
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| D | LiveDebugVariables.cpp | 442 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
448 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
882 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
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| D | TargetRegisterInfo.cpp | 264 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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| D | PHIElimination.cpp | 200 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
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| D | MachineBasicBlock.cpp | 368 unsigned VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
375 unsigned VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
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| D | InlineSpiller.cpp | 854 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, in reMaterializeFor()
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| /external/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
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| D | LiveIntervalUnion.h | 107 LiveInterval *VirtReg; variable
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| D | ScheduleDAGInstrs.h | 35 unsigned VirtReg; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 217 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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