1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class wraps target description classes used by the various code
11 // generation TableGen backends. This makes it easier to access the data and
12 // provides a single place that needs to check it for validity. All of these
13 // classes abort on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "CodeGenTarget.h"
18 #include "CodeGenIntrinsics.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/TableGen/Error.h"
24 #include "llvm/TableGen/Record.h"
25 #include <algorithm>
26 using namespace llvm;
27
28 static cl::opt<unsigned>
29 AsmParserNum("asmparsernum", cl::init(0),
30 cl::desc("Make -gen-asm-parser emit assembly parser #N"));
31
32 static cl::opt<unsigned>
33 AsmWriterNum("asmwriternum", cl::init(0),
34 cl::desc("Make -gen-asm-writer emit assembly writer #N"));
35
36 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
37 /// record corresponds to.
getValueType(Record * Rec)38 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
40 }
41
getName(MVT::SimpleValueType T)42 std::string llvm::getName(MVT::SimpleValueType T) {
43 switch (T) {
44 case MVT::Other: return "UNKNOWN";
45 case MVT::iPTR: return "TLI.getPointerTy()";
46 case MVT::iPTRAny: return "TLI.getPointerTy()";
47 default: return getEnumName(T);
48 }
49 }
50
getEnumName(MVT::SimpleValueType T)51 std::string llvm::getEnumName(MVT::SimpleValueType T) {
52 switch (T) {
53 case MVT::Other: return "MVT::Other";
54 case MVT::i1: return "MVT::i1";
55 case MVT::i8: return "MVT::i8";
56 case MVT::i16: return "MVT::i16";
57 case MVT::i32: return "MVT::i32";
58 case MVT::i64: return "MVT::i64";
59 case MVT::i128: return "MVT::i128";
60 case MVT::iAny: return "MVT::iAny";
61 case MVT::fAny: return "MVT::fAny";
62 case MVT::vAny: return "MVT::vAny";
63 case MVT::f16: return "MVT::f16";
64 case MVT::f32: return "MVT::f32";
65 case MVT::f64: return "MVT::f64";
66 case MVT::f80: return "MVT::f80";
67 case MVT::f128: return "MVT::f128";
68 case MVT::ppcf128: return "MVT::ppcf128";
69 case MVT::x86mmx: return "MVT::x86mmx";
70 case MVT::Glue: return "MVT::Glue";
71 case MVT::isVoid: return "MVT::isVoid";
72 case MVT::v2i1: return "MVT::v2i1";
73 case MVT::v4i1: return "MVT::v4i1";
74 case MVT::v8i1: return "MVT::v8i1";
75 case MVT::v16i1: return "MVT::v16i1";
76 case MVT::v32i1: return "MVT::v32i1";
77 case MVT::v64i1: return "MVT::v64i1";
78 case MVT::v1i8: return "MVT::v1i8";
79 case MVT::v2i8: return "MVT::v2i8";
80 case MVT::v4i8: return "MVT::v4i8";
81 case MVT::v8i8: return "MVT::v8i8";
82 case MVT::v16i8: return "MVT::v16i8";
83 case MVT::v32i8: return "MVT::v32i8";
84 case MVT::v64i8: return "MVT::v64i8";
85 case MVT::v1i16: return "MVT::v1i16";
86 case MVT::v2i16: return "MVT::v2i16";
87 case MVT::v4i16: return "MVT::v4i16";
88 case MVT::v8i16: return "MVT::v8i16";
89 case MVT::v16i16: return "MVT::v16i16";
90 case MVT::v32i16: return "MVT::v32i16";
91 case MVT::v1i32: return "MVT::v1i32";
92 case MVT::v2i32: return "MVT::v2i32";
93 case MVT::v4i32: return "MVT::v4i32";
94 case MVT::v8i32: return "MVT::v8i32";
95 case MVT::v16i32: return "MVT::v16i32";
96 case MVT::v1i64: return "MVT::v1i64";
97 case MVT::v2i64: return "MVT::v2i64";
98 case MVT::v4i64: return "MVT::v4i64";
99 case MVT::v8i64: return "MVT::v8i64";
100 case MVT::v16i64: return "MVT::v16i64";
101 case MVT::v2f16: return "MVT::v2f16";
102 case MVT::v4f16: return "MVT::v4f16";
103 case MVT::v8f16: return "MVT::v8f16";
104 case MVT::v1f32: return "MVT::v1f32";
105 case MVT::v2f32: return "MVT::v2f32";
106 case MVT::v4f32: return "MVT::v4f32";
107 case MVT::v8f32: return "MVT::v8f32";
108 case MVT::v16f32: return "MVT::v16f32";
109 case MVT::v1f64: return "MVT::v1f64";
110 case MVT::v2f64: return "MVT::v2f64";
111 case MVT::v4f64: return "MVT::v4f64";
112 case MVT::v8f64: return "MVT::v8f64";
113 case MVT::Metadata: return "MVT::Metadata";
114 case MVT::iPTR: return "MVT::iPTR";
115 case MVT::iPTRAny: return "MVT::iPTRAny";
116 case MVT::Untyped: return "MVT::Untyped";
117 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
118 }
119 }
120
121 /// getQualifiedName - Return the name of the specified record, with a
122 /// namespace qualifier if the record contains one.
123 ///
getQualifiedName(const Record * R)124 std::string llvm::getQualifiedName(const Record *R) {
125 std::string Namespace;
126 if (R->getValue("Namespace"))
127 Namespace = R->getValueAsString("Namespace");
128 if (Namespace.empty()) return R->getName();
129 return Namespace + "::" + R->getName();
130 }
131
132
133 /// getTarget - Return the current instance of the Target class.
134 ///
CodeGenTarget(RecordKeeper & records)135 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
136 : Records(records), RegBank(nullptr), SchedModels(nullptr) {
137 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
138 if (Targets.size() == 0)
139 PrintFatalError("ERROR: No 'Target' subclasses defined!");
140 if (Targets.size() != 1)
141 PrintFatalError("ERROR: Multiple subclasses of Target defined!");
142 TargetRec = Targets[0];
143 }
144
~CodeGenTarget()145 CodeGenTarget::~CodeGenTarget() {
146 DeleteContainerSeconds(Instructions);
147 delete RegBank;
148 delete SchedModels;
149 }
150
getName() const151 const std::string &CodeGenTarget::getName() const {
152 return TargetRec->getName();
153 }
154
getInstNamespace() const155 std::string CodeGenTarget::getInstNamespace() const {
156 for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
157 // Make sure not to pick up "TargetOpcode" by accidentally getting
158 // the namespace off the PHI instruction or something.
159 if ((*i)->Namespace != "TargetOpcode")
160 return (*i)->Namespace;
161 }
162
163 return "";
164 }
165
getInstructionSet() const166 Record *CodeGenTarget::getInstructionSet() const {
167 return TargetRec->getValueAsDef("InstructionSet");
168 }
169
170
171 /// getAsmParser - Return the AssemblyParser definition for this target.
172 ///
getAsmParser() const173 Record *CodeGenTarget::getAsmParser() const {
174 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
175 if (AsmParserNum >= LI.size())
176 PrintFatalError("Target does not have an AsmParser #" +
177 Twine(AsmParserNum) + "!");
178 return LI[AsmParserNum];
179 }
180
181 /// getAsmParserVariant - Return the AssmblyParserVariant definition for
182 /// this target.
183 ///
getAsmParserVariant(unsigned i) const184 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
185 std::vector<Record*> LI =
186 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
187 if (i >= LI.size())
188 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
189 "!");
190 return LI[i];
191 }
192
193 /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
194 /// available for this target.
195 ///
getAsmParserVariantCount() const196 unsigned CodeGenTarget::getAsmParserVariantCount() const {
197 std::vector<Record*> LI =
198 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
199 return LI.size();
200 }
201
202 /// getAsmWriter - Return the AssemblyWriter definition for this target.
203 ///
getAsmWriter() const204 Record *CodeGenTarget::getAsmWriter() const {
205 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
206 if (AsmWriterNum >= LI.size())
207 PrintFatalError("Target does not have an AsmWriter #" +
208 Twine(AsmWriterNum) + "!");
209 return LI[AsmWriterNum];
210 }
211
getRegBank() const212 CodeGenRegBank &CodeGenTarget::getRegBank() const {
213 if (!RegBank)
214 RegBank = new CodeGenRegBank(Records);
215 return *RegBank;
216 }
217
ReadRegAltNameIndices() const218 void CodeGenTarget::ReadRegAltNameIndices() const {
219 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
220 std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord());
221 }
222
223 /// getRegisterByName - If there is a register with the specific AsmName,
224 /// return it.
getRegisterByName(StringRef Name) const225 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
226 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
227 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
228 if (I == Regs.end())
229 return nullptr;
230 return I->second;
231 }
232
233 std::vector<MVT::SimpleValueType> CodeGenTarget::
getRegisterVTs(Record * R) const234 getRegisterVTs(Record *R) const {
235 const CodeGenRegister *Reg = getRegBank().getReg(R);
236 std::vector<MVT::SimpleValueType> Result;
237 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses();
238 for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
239 const CodeGenRegisterClass &RC = *RCs[i];
240 if (RC.contains(Reg)) {
241 ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes();
242 Result.insert(Result.end(), InVTs.begin(), InVTs.end());
243 }
244 }
245
246 // Remove duplicates.
247 array_pod_sort(Result.begin(), Result.end());
248 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
249 return Result;
250 }
251
252
ReadLegalValueTypes() const253 void CodeGenTarget::ReadLegalValueTypes() const {
254 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses();
255 for (unsigned i = 0, e = RCs.size(); i != e; ++i)
256 for (unsigned ri = 0, re = RCs[i]->VTs.size(); ri != re; ++ri)
257 LegalValueTypes.push_back(RCs[i]->VTs[ri]);
258
259 // Remove duplicates.
260 std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
261 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
262 LegalValueTypes.end()),
263 LegalValueTypes.end());
264 }
265
getSchedModels() const266 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
267 if (!SchedModels)
268 SchedModels = new CodeGenSchedModels(Records, *this);
269 return *SchedModels;
270 }
271
ReadInstructions() const272 void CodeGenTarget::ReadInstructions() const {
273 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
274 if (Insts.size() <= 2)
275 PrintFatalError("No 'Instruction' subclasses defined!");
276
277 // Parse the instructions defined in the .td file.
278 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
279 Instructions[Insts[i]] = new CodeGenInstruction(Insts[i]);
280 }
281
282 static const CodeGenInstruction *
GetInstByName(const char * Name,const DenseMap<const Record *,CodeGenInstruction * > & Insts,RecordKeeper & Records)283 GetInstByName(const char *Name,
284 const DenseMap<const Record*, CodeGenInstruction*> &Insts,
285 RecordKeeper &Records) {
286 const Record *Rec = Records.getDef(Name);
287
288 DenseMap<const Record*, CodeGenInstruction*>::const_iterator
289 I = Insts.find(Rec);
290 if (!Rec || I == Insts.end())
291 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
292 return I->second;
293 }
294
295 /// \brief Return all of the instructions defined by the target, ordered by
296 /// their enum value.
ComputeInstrsByEnum() const297 void CodeGenTarget::ComputeInstrsByEnum() const {
298 // The ordering here must match the ordering in TargetOpcodes.h.
299 static const char *const FixedInstrs[] = {
300 "PHI", "INLINEASM", "CFI_INSTRUCTION", "EH_LABEL",
301 "GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
302 "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
303 "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
304 "LIFETIME_END", "STACKMAP", "PATCHPOINT", nullptr};
305 const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
306 for (const char *const *p = FixedInstrs; *p; ++p) {
307 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
308 assert(Instr && "Missing target independent instruction");
309 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
310 InstrsByEnum.push_back(Instr);
311 }
312 unsigned EndOfPredefines = InstrsByEnum.size();
313
314 for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
315 I = Insts.begin(), E = Insts.end(); I != E; ++I) {
316 const CodeGenInstruction *CGI = I->second;
317 if (CGI->Namespace != "TargetOpcode")
318 InstrsByEnum.push_back(CGI);
319 }
320
321 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
322
323 // All of the instructions are now in random order based on the map iteration.
324 // Sort them by name.
325 std::sort(InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
326 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
327 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
328 });
329 }
330
331
332 /// isLittleEndianEncoding - Return whether this target encodes its instruction
333 /// in little-endian format, i.e. bits laid out in the order [0..n]
334 ///
isLittleEndianEncoding() const335 bool CodeGenTarget::isLittleEndianEncoding() const {
336 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
337 }
338
339 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
340 /// encodings, reverse the bit order of all instructions.
reverseBitsForLittleEndianEncoding()341 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
342 if (!isLittleEndianEncoding())
343 return;
344
345 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
346 for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
347 I != E; ++I) {
348 Record *R = *I;
349 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
350 R->getValueAsBit("isPseudo"))
351 continue;
352
353 BitsInit *BI = R->getValueAsBitsInit("Inst");
354
355 unsigned numBits = BI->getNumBits();
356
357 SmallVector<Init *, 16> NewBits(numBits);
358
359 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
360 unsigned bitSwapIdx = numBits - bit - 1;
361 Init *OrigBit = BI->getBit(bit);
362 Init *BitSwap = BI->getBit(bitSwapIdx);
363 NewBits[bit] = BitSwap;
364 NewBits[bitSwapIdx] = OrigBit;
365 }
366 if (numBits % 2) {
367 unsigned middle = (numBits + 1) / 2;
368 NewBits[middle] = BI->getBit(middle);
369 }
370
371 BitsInit *NewBI = BitsInit::get(NewBits);
372
373 // Update the bits in reversed order so that emitInstrOpBits will get the
374 // correct endianness.
375 R->getValue("Inst")->setValue(NewBI);
376 }
377 }
378
379 /// guessInstructionProperties - Return true if it's OK to guess instruction
380 /// properties instead of raising an error.
381 ///
382 /// This is configurable as a temporary migration aid. It will eventually be
383 /// permanently false.
guessInstructionProperties() const384 bool CodeGenTarget::guessInstructionProperties() const {
385 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
386 }
387
388 //===----------------------------------------------------------------------===//
389 // ComplexPattern implementation
390 //
ComplexPattern(Record * R)391 ComplexPattern::ComplexPattern(Record *R) {
392 Ty = ::getValueType(R->getValueAsDef("Ty"));
393 NumOperands = R->getValueAsInt("NumOperands");
394 SelectFunc = R->getValueAsString("SelectFunc");
395 RootNodes = R->getValueAsListOfDefs("RootNodes");
396
397 // Parse the properties.
398 Properties = 0;
399 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
400 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
401 if (PropList[i]->getName() == "SDNPHasChain") {
402 Properties |= 1 << SDNPHasChain;
403 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
404 Properties |= 1 << SDNPOptInGlue;
405 } else if (PropList[i]->getName() == "SDNPMayStore") {
406 Properties |= 1 << SDNPMayStore;
407 } else if (PropList[i]->getName() == "SDNPMayLoad") {
408 Properties |= 1 << SDNPMayLoad;
409 } else if (PropList[i]->getName() == "SDNPSideEffect") {
410 Properties |= 1 << SDNPSideEffect;
411 } else if (PropList[i]->getName() == "SDNPMemOperand") {
412 Properties |= 1 << SDNPMemOperand;
413 } else if (PropList[i]->getName() == "SDNPVariadic") {
414 Properties |= 1 << SDNPVariadic;
415 } else if (PropList[i]->getName() == "SDNPWantRoot") {
416 Properties |= 1 << SDNPWantRoot;
417 } else if (PropList[i]->getName() == "SDNPWantParent") {
418 Properties |= 1 << SDNPWantParent;
419 } else {
420 errs() << "Unsupported SD Node property '" << PropList[i]->getName()
421 << "' on ComplexPattern '" << R->getName() << "'!\n";
422 exit(1);
423 }
424 }
425
426 //===----------------------------------------------------------------------===//
427 // CodeGenIntrinsic Implementation
428 //===----------------------------------------------------------------------===//
429
LoadIntrinsics(const RecordKeeper & RC,bool TargetOnly)430 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
431 bool TargetOnly) {
432 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
433
434 std::vector<CodeGenIntrinsic> Result;
435
436 for (unsigned i = 0, e = I.size(); i != e; ++i) {
437 bool isTarget = I[i]->getValueAsBit("isTarget");
438 if (isTarget == TargetOnly)
439 Result.push_back(CodeGenIntrinsic(I[i]));
440 }
441 return Result;
442 }
443
CodeGenIntrinsic(Record * R)444 CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
445 TheDef = R;
446 std::string DefName = R->getName();
447 ModRef = ReadWriteMem;
448 isOverloaded = false;
449 isCommutative = false;
450 canThrow = false;
451 isNoReturn = false;
452 isNoDuplicate = false;
453
454 if (DefName.size() <= 4 ||
455 std::string(DefName.begin(), DefName.begin() + 4) != "int_")
456 PrintFatalError("Intrinsic '" + DefName + "' does not start with 'int_'!");
457
458 EnumName = std::string(DefName.begin()+4, DefName.end());
459
460 if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
461 GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
462 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field.
463 MSBuiltinName = R->getValueAsString("MSBuiltinName");
464
465 TargetPrefix = R->getValueAsString("TargetPrefix");
466 Name = R->getValueAsString("LLVMName");
467
468 if (Name == "") {
469 // If an explicit name isn't specified, derive one from the DefName.
470 Name = "llvm.";
471
472 for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
473 Name += (EnumName[i] == '_') ? '.' : EnumName[i];
474 } else {
475 // Verify it starts with "llvm.".
476 if (Name.size() <= 5 ||
477 std::string(Name.begin(), Name.begin() + 5) != "llvm.")
478 PrintFatalError("Intrinsic '" + DefName + "'s name does not start with 'llvm.'!");
479 }
480
481 // If TargetPrefix is specified, make sure that Name starts with
482 // "llvm.<targetprefix>.".
483 if (!TargetPrefix.empty()) {
484 if (Name.size() < 6+TargetPrefix.size() ||
485 std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
486 != (TargetPrefix + "."))
487 PrintFatalError("Intrinsic '" + DefName + "' does not start with 'llvm." +
488 TargetPrefix + ".'!");
489 }
490
491 // Parse the list of return types.
492 std::vector<MVT::SimpleValueType> OverloadedVTs;
493 ListInit *TypeList = R->getValueAsListInit("RetTypes");
494 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
495 Record *TyEl = TypeList->getElementAsRecord(i);
496 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
497 MVT::SimpleValueType VT;
498 if (TyEl->isSubClassOf("LLVMMatchType")) {
499 unsigned MatchTy = TyEl->getValueAsInt("Number");
500 assert(MatchTy < OverloadedVTs.size() &&
501 "Invalid matching number!");
502 VT = OverloadedVTs[MatchTy];
503 // It only makes sense to use the extended and truncated vector element
504 // variants with iAny types; otherwise, if the intrinsic is not
505 // overloaded, all the types can be specified directly.
506 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
507 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
508 VT == MVT::iAny || VT == MVT::vAny) &&
509 "Expected iAny or vAny type");
510 } else {
511 VT = getValueType(TyEl->getValueAsDef("VT"));
512 }
513 if (MVT(VT).isOverloaded()) {
514 OverloadedVTs.push_back(VT);
515 isOverloaded = true;
516 }
517
518 // Reject invalid types.
519 if (VT == MVT::isVoid)
520 PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
521
522 IS.RetVTs.push_back(VT);
523 IS.RetTypeDefs.push_back(TyEl);
524 }
525
526 // Parse the list of parameter types.
527 TypeList = R->getValueAsListInit("ParamTypes");
528 for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
529 Record *TyEl = TypeList->getElementAsRecord(i);
530 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
531 MVT::SimpleValueType VT;
532 if (TyEl->isSubClassOf("LLVMMatchType")) {
533 unsigned MatchTy = TyEl->getValueAsInt("Number");
534 assert(MatchTy < OverloadedVTs.size() &&
535 "Invalid matching number!");
536 VT = OverloadedVTs[MatchTy];
537 // It only makes sense to use the extended and truncated vector element
538 // variants with iAny types; otherwise, if the intrinsic is not
539 // overloaded, all the types can be specified directly.
540 assert(((!TyEl->isSubClassOf("LLVMExtendedType") &&
541 !TyEl->isSubClassOf("LLVMTruncatedType")) ||
542 VT == MVT::iAny || VT == MVT::vAny) &&
543 "Expected iAny or vAny type");
544 } else
545 VT = getValueType(TyEl->getValueAsDef("VT"));
546
547 if (MVT(VT).isOverloaded()) {
548 OverloadedVTs.push_back(VT);
549 isOverloaded = true;
550 }
551
552 // Reject invalid types.
553 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/)
554 PrintFatalError("Intrinsic '" + DefName + " has void in result type list!");
555
556 IS.ParamVTs.push_back(VT);
557 IS.ParamTypeDefs.push_back(TyEl);
558 }
559
560 // Parse the intrinsic properties.
561 ListInit *PropList = R->getValueAsListInit("Properties");
562 for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
563 Record *Property = PropList->getElementAsRecord(i);
564 assert(Property->isSubClassOf("IntrinsicProperty") &&
565 "Expected a property!");
566
567 if (Property->getName() == "IntrNoMem")
568 ModRef = NoMem;
569 else if (Property->getName() == "IntrReadArgMem")
570 ModRef = ReadArgMem;
571 else if (Property->getName() == "IntrReadMem")
572 ModRef = ReadMem;
573 else if (Property->getName() == "IntrReadWriteArgMem")
574 ModRef = ReadWriteArgMem;
575 else if (Property->getName() == "Commutative")
576 isCommutative = true;
577 else if (Property->getName() == "Throws")
578 canThrow = true;
579 else if (Property->getName() == "IntrNoDuplicate")
580 isNoDuplicate = true;
581 else if (Property->getName() == "IntrNoReturn")
582 isNoReturn = true;
583 else if (Property->isSubClassOf("NoCapture")) {
584 unsigned ArgNo = Property->getValueAsInt("ArgNo");
585 ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
586 } else if (Property->isSubClassOf("ReadOnly")) {
587 unsigned ArgNo = Property->getValueAsInt("ArgNo");
588 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly));
589 } else if (Property->isSubClassOf("ReadNone")) {
590 unsigned ArgNo = Property->getValueAsInt("ArgNo");
591 ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone));
592 } else
593 llvm_unreachable("Unknown property!");
594 }
595
596 // Sort the argument attributes for later benefit.
597 std::sort(ArgumentAttributes.begin(), ArgumentAttributes.end());
598 }
599