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Searched defs:instruction (Results 1 – 25 of 202) sorted by relevance

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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/
DInstructionWriter.java80 public void write(@Nonnull Instruction10t instruction) { in write()
89 public void write(@Nonnull Instruction10x instruction) { in write()
98 public void write(@Nonnull Instruction11n instruction) { in write()
107 public void write(@Nonnull Instruction11x instruction) { in write()
116 public void write(@Nonnull Instruction12x instruction) { in write()
125 public void write(@Nonnull Instruction20bc instruction) { in write()
135 public void write(@Nonnull Instruction20t instruction) { in write()
145 public void write(@Nonnull Instruction21c instruction) { in write()
155 public void write(@Nonnull Instruction21ih instruction) { in write()
165 public void write(@Nonnull Instruction21lh instruction) { in write()
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/external/valgrind/main/none/tests/mips64/
Dmacro_load_store.h3 #define TEST1(instruction, offset, mem) \ argument
21 #define TEST2(instruction, offset) \ argument
47 #define TEST3(instruction, offset, mem) \ argument
65 #define TEST3w(instruction, offset, mem) \ argument
83 #define TEST4(instruction, offset) \ argument
104 #define TEST5(instruction, offset, mem) \ argument
121 #define TEST5w(instruction, offset, mem) \ argument
138 #define TEST6(instruction, offset) \ argument
Dmacro_int.h1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \ argument
19 #define TEST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TEST3(instruction, RSval, RD, RS) \ argument
51 #define TEST4(instruction, RSval, RTval, RS, RT) \ argument
71 #define TEST5(instruction, RSval, RTval, RS, RT) \ argument
91 #define TEST6(instruction, imm, RT) \ argument
Drotate_swap.c3 #define TESTINST_DROTR(instruction, in, SA) \ argument
19 #define TESTINST_DROTRV(instruction, in, SA) \ argument
36 #define TESTINST_DSWAP(instruction, in) \ argument
Dmove_instructions.c92 #define TEST3(instruction, FD, FS, cc, offset) \ argument
116 #define TEST3d(instruction, FD, FS, cc, offset) \ argument
139 #define TEST4(instruction, offset, RTval, FD, FS, RT) \ argument
158 #define TEST4d(instruction, offset, RTval, FD, FS, RT) \ argument
177 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
201 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
224 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
246 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
130 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument
152 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
Dcvm_ins.c70 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \ argument
85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ argument
101 #define TESTINST3(instruction, RSVal, RT, RS,imm) \ argument
/external/valgrind/main/none/tests/mips32/
DMoveIns.c25 #define TESTINSNMOVE(instruction, offset, FS, RT) \ argument
44 #define TESTINSNMOVEd(instruction, offset, FS, RT) \ argument
63 #define TESTINSNMOVEt(instruction, offset, FS, RT) \ argument
82 #define TESTINSNMOVEtd(instruction, offset, FS, RT) \ argument
101 #define TESTINSNMOVE1s(instruction, offset, FD, FS) \ argument
120 #define TESTINSNMOVE1d(instruction, offset, FD, FS) \ argument
139 #define TESTINSNMOVE2(instruction, RDval, RSval, RD, RS, cc) \ argument
161 #define TESTINSNMOVE2s(instruction, FD, FS, cc, offset) \ argument
185 #define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \ argument
210 #define TESTINSNMOVE2d(instruction, FD, FS, cc, offset) \ argument
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Dfpu_branches.c42 #define TESTINST1s(instruction, RDval) \ argument
64 #define TESTINST1d(instruction, RDval) \ argument
86 #define TESTINST2s(instruction, RDval) \ argument
107 #define TESTINST2d(instruction, RDval) \ argument
128 #define TESTINST_CONDs(instruction, RDval) \ argument
150 #define TESTINST_CONDd(instruction, RDval) \ argument
Dmips32_dspr2.c39 #define TESTDSPINST_RD_RT_DSPC(instruction, RTval, RD, RT) \ argument
59 #define TESTDSPINST_RD_RT_NODSPC(instruction, RTval, RD, RT) \ argument
75 #define TESTDSPINST_RD_RT_RS_NODSPC(instruction, RTval, RSval) \ argument
92 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
113 #define TESTDSPINST_BPOSGE32(instruction, RDval, POSval, RD, POSreg) \ argument
134 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
152 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
170 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
198 #define TESTDSPINST_AC_RS_RT_NODSPC(instruction, HIval, LOval, RSval, RTval) \ argument
222 #define TESTDSPINST_EXT(instruction, ac, RT, HIval, LOval, size, pos) \ argument
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Dmips32_dsp.c39 #define TESTDSPINST_RD_RT_DSPC(instruction, RTval, RD, RT) \ argument
59 #define TESTDSPINST_RD_RT_NODSPC(instruction, RTval, RD, RT) \ argument
76 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
97 #define TESTDSPINST_BPOSGE32(instruction, RDval, POSval, RD, POSreg) \ argument
119 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
137 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
155 #define TESTDSPINST_AC_RS_RT_DSPC(instruction, ac, RSval, RTval, HIval, LOval, \ argument
183 #define TESTDSPINST_AC_RS_RT_NODSPC(instruction, ac, RSval, RTval, HIval, \ argument
207 #define TESTDSPINST_EXT(instruction, ac, RT, HIval, LOval, size, pos) \ argument
230 #define TESTDSPINST_EXTV(instruction, ac, RT, HIval, LOval, RS, RSval, pos) \ argument
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DMIPS32int.c3 #define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \ argument
20 #define TESTINST2(instruction, RSval, imm, RT, RS) \ argument
35 #define TESTINST3(instruction, RSval, RD, RS) \ argument
50 #define TESTINST3a(instruction, RSval, RTval, RS, RT) \ argument
71 #define TESTINST4(instruction, RTval, RSval, RT, RS, pos, size) \ argument
95 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
Dvfp.c49 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
69 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
91 #define TESTINSN5LOADw(instruction, RTval, offset, RT) \ argument
110 #define TESTINSN6LOADw(instruction, indexVal, fd, index, base) \ argument
128 #define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \ argument
146 #define TESTINSN6LOADd(instruction, indexVal, fd, index, base) \ argument
Dbranches.c114 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
135 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
155 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
179 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
200 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument
220 #define TESTINST6l(instruction, RDval, RSval, RD, RS) \ argument
/external/valgrind/main/none/tests/arm/
Dvfp.c62 #define TESTINSN_vmovf32_imm(instruction, DD, imm) \ argument
77 #define TESTINSN_vmov_core_single(instruction, RN, SD, SDval) \ argument
95 #define TESTINSN_vmov_single_core(instruction, SD, RN, RNval) \ argument
113 #define TESTINSN_vmov_2core_2single(instruction, RD1, RD2, SN, SM, SNval, SMval) \ argument
134 #define TESTINSN_vmov_2single_2core(instruction, SD1, SD2, RN, RM, RNval, RMval) \ argument
154 #define TESTINSN_vmov_double_2core(instruction, DD, RN, RM, RNval, RMval) \ argument
173 #define TESTINSN_vmov_2core_double(instruction, RD1, RD2, DN, DNval0, DNval1) \ argument
193 #define TESTINSN_un_f64(instruction, DD, DM, DMtype, DMval0, DMval1) \ argument
210 #define TESTINSN_un_f32(instruction, SD, SM, SMtype, SMval) \ argument
227 #define TESTINSN_un_cvt_ds(instruction, DD, SM, SMval) \ argument
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Dv6intThumb.c19 #define TESTINST1(instruction, RD, cvin) \ argument
47 #define TESTINST1x(instruction, RDval, RD, cvin) \ argument
74 #define TESTINST2(instruction, RMval, RD, RM, cvin) \ argument
106 #define TESTINST2x(instruction, RDval, RMval, RD, RM, cvin) \ argument
135 #define TESTINST3(instruction, RMval, RNval, RD, RM, RN, cvin) \ argument
162 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \ argument
190 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \ argument
222 #define TESTINSTPCMISALIGNED(instruction, RD, label, cvin) \ argument
260 #define TESTINSTPCMISALIGNED_DWORDOUT(instruction, label, cvin, extratrash) \ argument
298 #define TESTINSTPCMISALIGNED_2OUT(instruction, RD, RD2, label, cvin) \ argument
Dneon64.c52 #define TESTINSN_imm(instruction, QD, imm) \ argument
86 #define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \ argument
123 #define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \ argument
169 #define TESTINSN_core_to_scalar(instruction, QD, QM, QMval) \ argument
187 #define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \ argument
205 #define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \ argument
233 #define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \ argument
258 #define TESTINSN_VLDn_WB(instruction, QD1, QD2, QD3, QD4) \ argument
288 #define TESTINSN_VSTn_WB(instruction, QD1, QD2, QD3, QD4) \ argument
314 #define TESTINSN_VLDn_RI(instruction, QD1, QD2, QD3, QD4, RM, RMval) \ argument
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Dneon128.c51 #define TESTINSN_imm(instruction, QD, imm) \ argument
83 #define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \ argument
118 #define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \ argument
164 #define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ argument
202 #define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ argument
240 #define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \ argument
291 #define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \ argument
Dv6intARM.c9 #define TESTINST2(instruction, RMval, RD, RM, carryin) \ argument
41 #define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \ argument
70 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
100 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
Dv6media.c18 #define TESTINST2(instruction, RMval, RD, RM, carryin) \ argument
50 #define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \ argument
79 #define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \ argument
109 #define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \ argument
/external/proguard/src/proguard/optimize/evaluation/
DEvaluationSimplifier.java148 Instruction instruction = InstructionFactory.create(codeAttribute.code, in visitCodeAttribute0() local
378 Instruction instruction) in replaceAnyPushInstruction()
411 Instruction instruction) in replaceIntegerPushInstruction()
426 Instruction instruction, in replaceIntegerPushInstruction()
480 Instruction instruction) in replaceLongPushInstruction()
495 Instruction instruction, in replaceLongPushInstruction()
552 Instruction instruction) in replaceFloatPushInstruction()
567 Instruction instruction, in replaceFloatPushInstruction()
623 Instruction instruction) in replaceDoublePushInstruction()
638 Instruction instruction, in replaceDoublePushInstruction()
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/external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/
DPreInstructionRegisterInfoMethodItem.java109 …RegisterRangeInstruction instruction = (RegisterRangeInstruction)analyzedInstruction.getInstructio… in addArgsRegs() local
114 …FiveRegisterInstruction instruction = (FiveRegisterInstruction)analyzedInstruction.getInstruction(… in addArgsRegs() local
133 …ThreeRegisterInstruction instruction = (ThreeRegisterInstruction)analyzedInstruction.getInstructio… in addArgsRegs() local
138 … TwoRegisterInstruction instruction = (TwoRegisterInstruction)analyzedInstruction.getInstruction(); in addArgsRegs() local
142 … OneRegisterInstruction instruction = (OneRegisterInstruction)analyzedInstruction.getInstruction(); in addArgsRegs() local
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/raw/
DCodeItem.java121 Instruction instruction = DexBackedInstruction.readFrom(reader); in makeAnnotator() local
249 …rivate void annotateInstruction10x(@Nonnull AnnotatedBytes out, @Nonnull Instruction instruction) { in makeAnnotator()
253 …ate void annotateInstruction35c(@Nonnull AnnotatedBytes out, @Nonnull Instruction35c instruction) { in makeAnnotator()
285 …ate void annotateInstruction3rc(@Nonnull AnnotatedBytes out, @Nonnull Instruction3rc instruction) { in makeAnnotator()
294 …te void annotateDefaultInstruction(@Nonnull AnnotatedBytes out, @Nonnull Instruction instruction) { in makeAnnotator()
350 …private void annotateArrayPayload(@Nonnull AnnotatedBytes out, @Nonnull ArrayPayload instruction) { in makeAnnotator()
385 @Nonnull PackedSwitchPayload instruction) { in makeAnnotator()
407 @Nonnull SparseSwitchPayload instruction) { in makeAnnotator()
/external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/
DAnalyzedInstruction.java46 protected Instruction instruction; field in AnalyzedInstruction
79 public AnalyzedInstruction(Instruction instruction, int instructionIndex, int registerCount) { in AnalyzedInstruction()
112 protected void setDeodexedInstruction(Instruction instruction) { in setDeodexedInstruction()

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