1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_INSTRUCTION_CODES_H_ 6 #define V8_COMPILER_INSTRUCTION_CODES_H_ 7 8 #if V8_TARGET_ARCH_ARM 9 #include "src/compiler/arm/instruction-codes-arm.h" 10 #elif V8_TARGET_ARCH_ARM64 11 #include "src/compiler/arm64/instruction-codes-arm64.h" 12 #elif V8_TARGET_ARCH_IA32 13 #include "src/compiler/ia32/instruction-codes-ia32.h" 14 #elif V8_TARGET_ARCH_X64 15 #include "src/compiler/x64/instruction-codes-x64.h" 16 #else 17 #define TARGET_ARCH_OPCODE_LIST(V) 18 #define TARGET_ADDRESSING_MODE_LIST(V) 19 #endif 20 #include "src/utils.h" 21 22 namespace v8 { 23 namespace internal { 24 25 class OStream; 26 27 namespace compiler { 28 29 // Target-specific opcodes that specify which assembly sequence to emit. 30 // Most opcodes specify a single instruction. 31 #define ARCH_OPCODE_LIST(V) \ 32 V(ArchCallCodeObject) \ 33 V(ArchCallJSFunction) \ 34 V(ArchJmp) \ 35 V(ArchNop) \ 36 V(ArchRet) \ 37 V(ArchTruncateDoubleToI) \ 38 TARGET_ARCH_OPCODE_LIST(V) 39 40 enum ArchOpcode { 41 #define DECLARE_ARCH_OPCODE(Name) k##Name, 42 ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE) 43 #undef DECLARE_ARCH_OPCODE 44 #define COUNT_ARCH_OPCODE(Name) +1 45 kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE) 46 #undef COUNT_ARCH_OPCODE 47 }; 48 49 OStream& operator<<(OStream& os, const ArchOpcode& ao); 50 51 // Addressing modes represent the "shape" of inputs to an instruction. 52 // Many instructions support multiple addressing modes. Addressing modes 53 // are encoded into the InstructionCode of the instruction and tell the 54 // code generator after register allocation which assembler method to call. 55 #define ADDRESSING_MODE_LIST(V) \ 56 V(None) \ 57 TARGET_ADDRESSING_MODE_LIST(V) 58 59 enum AddressingMode { 60 #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name, 61 ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE) 62 #undef DECLARE_ADDRESSING_MODE 63 #define COUNT_ADDRESSING_MODE(Name) +1 64 kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE) 65 #undef COUNT_ADDRESSING_MODE 66 }; 67 68 OStream& operator<<(OStream& os, const AddressingMode& am); 69 70 // The mode of the flags continuation (see below). 71 enum FlagsMode { kFlags_none = 0, kFlags_branch = 1, kFlags_set = 2 }; 72 73 OStream& operator<<(OStream& os, const FlagsMode& fm); 74 75 // The condition of flags continuation (see below). 76 enum FlagsCondition { 77 kEqual, 78 kNotEqual, 79 kSignedLessThan, 80 kSignedGreaterThanOrEqual, 81 kSignedLessThanOrEqual, 82 kSignedGreaterThan, 83 kUnsignedLessThan, 84 kUnsignedGreaterThanOrEqual, 85 kUnsignedLessThanOrEqual, 86 kUnsignedGreaterThan, 87 kUnorderedEqual, 88 kUnorderedNotEqual, 89 kUnorderedLessThan, 90 kUnorderedGreaterThanOrEqual, 91 kUnorderedLessThanOrEqual, 92 kUnorderedGreaterThan, 93 kOverflow, 94 kNotOverflow 95 }; 96 97 OStream& operator<<(OStream& os, const FlagsCondition& fc); 98 99 // The InstructionCode is an opaque, target-specific integer that encodes 100 // what code to emit for an instruction in the code generator. It is not 101 // interesting to the register allocator, as the inputs and flags on the 102 // instructions specify everything of interest. 103 typedef int32_t InstructionCode; 104 105 // Helpers for encoding / decoding InstructionCode into the fields needed 106 // for code generation. We encode the instruction, addressing mode, and flags 107 // continuation into a single InstructionCode which is stored as part of 108 // the instruction. 109 typedef BitField<ArchOpcode, 0, 7> ArchOpcodeField; 110 typedef BitField<AddressingMode, 7, 4> AddressingModeField; 111 typedef BitField<FlagsMode, 11, 2> FlagsModeField; 112 typedef BitField<FlagsCondition, 13, 5> FlagsConditionField; 113 typedef BitField<int, 13, 19> MiscField; 114 115 } // namespace compiler 116 } // namespace internal 117 } // namespace v8 118 119 #endif // V8_COMPILER_INSTRUCTION_CODES_H_ 120