1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
14 //
15 //===----------------------------------------------------------------------===//
16
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <string>
22
23 using namespace llvm;
24
25 #define MRM_MAPPING \
26 MAP(C0, 32) \
27 MAP(C1, 33) \
28 MAP(C2, 34) \
29 MAP(C3, 35) \
30 MAP(C4, 36) \
31 MAP(C8, 37) \
32 MAP(C9, 38) \
33 MAP(CA, 39) \
34 MAP(CB, 40) \
35 MAP(D0, 41) \
36 MAP(D1, 42) \
37 MAP(D4, 43) \
38 MAP(D5, 44) \
39 MAP(D6, 45) \
40 MAP(D8, 46) \
41 MAP(D9, 47) \
42 MAP(DA, 48) \
43 MAP(DB, 49) \
44 MAP(DC, 50) \
45 MAP(DD, 51) \
46 MAP(DE, 52) \
47 MAP(DF, 53) \
48 MAP(E0, 54) \
49 MAP(E1, 55) \
50 MAP(E2, 56) \
51 MAP(E3, 57) \
52 MAP(E4, 58) \
53 MAP(E5, 59) \
54 MAP(E8, 60) \
55 MAP(E9, 61) \
56 MAP(EA, 62) \
57 MAP(EB, 63) \
58 MAP(EC, 64) \
59 MAP(ED, 65) \
60 MAP(EE, 66) \
61 MAP(F0, 67) \
62 MAP(F1, 68) \
63 MAP(F2, 69) \
64 MAP(F3, 70) \
65 MAP(F4, 71) \
66 MAP(F5, 72) \
67 MAP(F6, 73) \
68 MAP(F7, 74) \
69 MAP(F8, 75) \
70 MAP(F9, 76) \
71 MAP(FA, 77) \
72 MAP(FB, 78) \
73 MAP(FC, 79) \
74 MAP(FD, 80) \
75 MAP(FE, 81) \
76 MAP(FF, 82)
77
78 // A clone of X86 since we can't depend on something that is generated.
79 namespace X86Local {
80 enum {
81 Pseudo = 0,
82 RawFrm = 1,
83 AddRegFrm = 2,
84 MRMDestReg = 3,
85 MRMDestMem = 4,
86 MRMSrcReg = 5,
87 MRMSrcMem = 6,
88 RawFrmMemOffs = 7,
89 RawFrmSrc = 8,
90 RawFrmDst = 9,
91 RawFrmDstSrc = 10,
92 RawFrmImm8 = 11,
93 RawFrmImm16 = 12,
94 MRMXr = 14, MRMXm = 15,
95 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
96 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
97 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
98 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
99 #define MAP(from, to) MRM_##from = to,
100 MRM_MAPPING
101 #undef MAP
102 lastMRM
103 };
104
105 enum {
106 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
107 };
108
109 enum {
110 PS = 1, PD = 2, XS = 3, XD = 4
111 };
112
113 enum {
114 VEX = 1, XOP = 2, EVEX = 3
115 };
116
117 enum {
118 OpSize16 = 1, OpSize32 = 2
119 };
120 }
121
122 using namespace X86Disassembler;
123
124 /// isRegFormat - Indicates whether a particular form requires the Mod field of
125 /// the ModR/M byte to be 0b11.
126 ///
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that Mod must be 0b11, false
129 /// otherwise.
isRegFormat(uint8_t form)130 static bool isRegFormat(uint8_t form) {
131 return (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMSrcReg ||
133 form == X86Local::MRMXr ||
134 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
135 }
136
137 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
138 /// Useful for switch statements and the like.
139 ///
140 /// @param init - A reference to the BitsInit to be decoded.
141 /// @return - The field, with the first bit in the BitsInit as the lowest
142 /// order bit.
byteFromBitsInit(BitsInit & init)143 static uint8_t byteFromBitsInit(BitsInit &init) {
144 int width = init.getNumBits();
145
146 assert(width <= 8 && "Field is too large for uint8_t!");
147
148 int index;
149 uint8_t mask = 0x01;
150
151 uint8_t ret = 0;
152
153 for (index = 0; index < width; index++) {
154 if (static_cast<BitInit*>(init.getBit(index))->getValue())
155 ret |= mask;
156
157 mask <<= 1;
158 }
159
160 return ret;
161 }
162
163 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
164 /// name of the field.
165 ///
166 /// @param rec - The record from which to extract the value.
167 /// @param name - The name of the field in the record.
168 /// @return - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,const std::string & name)169 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
170 BitsInit* bits = rec->getValueAsBitsInit(name);
171 return byteFromBitsInit(*bits);
172 }
173
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)174 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
175 const CodeGenInstruction &insn,
176 InstrUID uid) {
177 UID = uid;
178
179 Rec = insn.TheDef;
180 Name = Rec->getName();
181 Spec = &tables.specForUID(UID);
182
183 if (!Rec->isSubClassOf("X86Inst")) {
184 ShouldBeEmitted = false;
185 return;
186 }
187
188 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
189 OpMap = byteFromRec(Rec, "OpMapBits");
190 Opcode = byteFromRec(Rec, "Opcode");
191 Form = byteFromRec(Rec, "FormBits");
192 Encoding = byteFromRec(Rec, "OpEncBits");
193
194 OpSize = byteFromRec(Rec, "OpSizeBits");
195 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
196 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
197 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
198 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
199 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
200 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
201 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
202 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
203 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
204 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
205 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
206 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
207 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
208
209 Name = Rec->getName();
210 AsmString = Rec->getValueAsString("AsmString");
211
212 Operands = &insn.Operands.OperandList;
213
214 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
215
216 // Check for 64-bit inst which does not require REX
217 Is32Bit = false;
218 Is64Bit = false;
219 // FIXME: Is there some better way to check for In64BitMode?
220 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
221 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
222 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
223 Predicates[i]->getName().find("In32Bit") != Name.npos) {
224 Is32Bit = true;
225 break;
226 }
227 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
228 Is64Bit = true;
229 break;
230 }
231 }
232
233 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
234 ShouldBeEmitted = false;
235 return;
236 }
237
238 // Special case since there is no attribute class for 64-bit and VEX
239 if (Name == "VMASKMOVDQU64") {
240 ShouldBeEmitted = false;
241 return;
242 }
243
244 ShouldBeEmitted = true;
245 }
246
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)247 void RecognizableInstr::processInstr(DisassemblerTables &tables,
248 const CodeGenInstruction &insn,
249 InstrUID uid)
250 {
251 // Ignore "asm parser only" instructions.
252 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
253 return;
254
255 RecognizableInstr recogInstr(tables, insn, uid);
256
257 if (recogInstr.shouldBeEmitted()) {
258 recogInstr.emitInstructionSpecifier();
259 recogInstr.emitDecodePath(tables);
260 }
261 }
262
263 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
264 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
265 (HasEVEX_KZ ? n##_KZ : \
266 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
267
insnContext() const268 InstructionContext RecognizableInstr::insnContext() const {
269 InstructionContext insnContext;
270
271 if (Encoding == X86Local::EVEX) {
272 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
273 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
274 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
275 }
276 // VEX_L & VEX_W
277 if (HasVEX_LPrefix && HasVEX_WPrefix) {
278 if (OpPrefix == X86Local::PD)
279 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
280 else if (OpPrefix == X86Local::XS)
281 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
282 else if (OpPrefix == X86Local::XD)
283 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
284 else if (OpPrefix == X86Local::PS)
285 insnContext = EVEX_KB(IC_EVEX_L_W);
286 else {
287 errs() << "Instruction does not use a prefix: " << Name << "\n";
288 llvm_unreachable("Invalid prefix");
289 }
290 } else if (HasVEX_LPrefix) {
291 // VEX_L
292 if (OpPrefix == X86Local::PD)
293 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
294 else if (OpPrefix == X86Local::XS)
295 insnContext = EVEX_KB(IC_EVEX_L_XS);
296 else if (OpPrefix == X86Local::XD)
297 insnContext = EVEX_KB(IC_EVEX_L_XD);
298 else if (OpPrefix == X86Local::PS)
299 insnContext = EVEX_KB(IC_EVEX_L);
300 else {
301 errs() << "Instruction does not use a prefix: " << Name << "\n";
302 llvm_unreachable("Invalid prefix");
303 }
304 }
305 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
306 // EVEX_L2 & VEX_W
307 if (OpPrefix == X86Local::PD)
308 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
309 else if (OpPrefix == X86Local::XS)
310 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
311 else if (OpPrefix == X86Local::XD)
312 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
313 else if (OpPrefix == X86Local::PS)
314 insnContext = EVEX_KB(IC_EVEX_L2_W);
315 else {
316 errs() << "Instruction does not use a prefix: " << Name << "\n";
317 llvm_unreachable("Invalid prefix");
318 }
319 } else if (HasEVEX_L2Prefix) {
320 // EVEX_L2
321 if (OpPrefix == X86Local::PD)
322 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
323 else if (OpPrefix == X86Local::XD)
324 insnContext = EVEX_KB(IC_EVEX_L2_XD);
325 else if (OpPrefix == X86Local::XS)
326 insnContext = EVEX_KB(IC_EVEX_L2_XS);
327 else if (OpPrefix == X86Local::PS)
328 insnContext = EVEX_KB(IC_EVEX_L2);
329 else {
330 errs() << "Instruction does not use a prefix: " << Name << "\n";
331 llvm_unreachable("Invalid prefix");
332 }
333 }
334 else if (HasVEX_WPrefix) {
335 // VEX_W
336 if (OpPrefix == X86Local::PD)
337 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
338 else if (OpPrefix == X86Local::XS)
339 insnContext = EVEX_KB(IC_EVEX_W_XS);
340 else if (OpPrefix == X86Local::XD)
341 insnContext = EVEX_KB(IC_EVEX_W_XD);
342 else if (OpPrefix == X86Local::PS)
343 insnContext = EVEX_KB(IC_EVEX_W);
344 else {
345 errs() << "Instruction does not use a prefix: " << Name << "\n";
346 llvm_unreachable("Invalid prefix");
347 }
348 }
349 // No L, no W
350 else if (OpPrefix == X86Local::PD)
351 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
352 else if (OpPrefix == X86Local::XD)
353 insnContext = EVEX_KB(IC_EVEX_XD);
354 else if (OpPrefix == X86Local::XS)
355 insnContext = EVEX_KB(IC_EVEX_XS);
356 else
357 insnContext = EVEX_KB(IC_EVEX);
358 /// eof EVEX
359 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
360 if (HasVEX_LPrefix && HasVEX_WPrefix) {
361 if (OpPrefix == X86Local::PD)
362 insnContext = IC_VEX_L_W_OPSIZE;
363 else if (OpPrefix == X86Local::XS)
364 insnContext = IC_VEX_L_W_XS;
365 else if (OpPrefix == X86Local::XD)
366 insnContext = IC_VEX_L_W_XD;
367 else if (OpPrefix == X86Local::PS)
368 insnContext = IC_VEX_L_W;
369 else {
370 errs() << "Instruction does not use a prefix: " << Name << "\n";
371 llvm_unreachable("Invalid prefix");
372 }
373 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
374 insnContext = IC_VEX_L_OPSIZE;
375 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
376 insnContext = IC_VEX_W_OPSIZE;
377 else if (OpPrefix == X86Local::PD)
378 insnContext = IC_VEX_OPSIZE;
379 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
380 insnContext = IC_VEX_L_XS;
381 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
382 insnContext = IC_VEX_L_XD;
383 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
384 insnContext = IC_VEX_W_XS;
385 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
386 insnContext = IC_VEX_W_XD;
387 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
388 insnContext = IC_VEX_W;
389 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
390 insnContext = IC_VEX_L;
391 else if (OpPrefix == X86Local::XD)
392 insnContext = IC_VEX_XD;
393 else if (OpPrefix == X86Local::XS)
394 insnContext = IC_VEX_XS;
395 else if (OpPrefix == X86Local::PS)
396 insnContext = IC_VEX;
397 else {
398 errs() << "Instruction does not use a prefix: " << Name << "\n";
399 llvm_unreachable("Invalid prefix");
400 }
401 } else if (Is64Bit || HasREX_WPrefix) {
402 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
403 insnContext = IC_64BIT_REXW_OPSIZE;
404 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
405 insnContext = IC_64BIT_XD_OPSIZE;
406 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
407 insnContext = IC_64BIT_XS_OPSIZE;
408 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
409 insnContext = IC_64BIT_OPSIZE;
410 else if (HasAdSizePrefix)
411 insnContext = IC_64BIT_ADSIZE;
412 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
413 insnContext = IC_64BIT_REXW_XS;
414 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
415 insnContext = IC_64BIT_REXW_XD;
416 else if (OpPrefix == X86Local::XD)
417 insnContext = IC_64BIT_XD;
418 else if (OpPrefix == X86Local::XS)
419 insnContext = IC_64BIT_XS;
420 else if (HasREX_WPrefix)
421 insnContext = IC_64BIT_REXW;
422 else
423 insnContext = IC_64BIT;
424 } else {
425 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
426 insnContext = IC_XD_OPSIZE;
427 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
428 insnContext = IC_XS_OPSIZE;
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
430 insnContext = IC_OPSIZE;
431 else if (HasAdSizePrefix)
432 insnContext = IC_ADSIZE;
433 else if (OpPrefix == X86Local::XD)
434 insnContext = IC_XD;
435 else if (OpPrefix == X86Local::XS)
436 insnContext = IC_XS;
437 else
438 insnContext = IC;
439 }
440
441 return insnContext;
442 }
443
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned & numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,uint8_t OpSize))444 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
445 unsigned &physicalOperandIndex,
446 unsigned &numPhysicalOperands,
447 const unsigned *operandMapping,
448 OperandEncoding (*encodingFromString)
449 (const std::string&,
450 uint8_t OpSize)) {
451 if (optional) {
452 if (physicalOperandIndex >= numPhysicalOperands)
453 return;
454 } else {
455 assert(physicalOperandIndex < numPhysicalOperands);
456 }
457
458 while (operandMapping[operandIndex] != operandIndex) {
459 Spec->operands[operandIndex].encoding = ENCODING_DUP;
460 Spec->operands[operandIndex].type =
461 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
462 ++operandIndex;
463 }
464
465 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
466
467 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
468 OpSize);
469 Spec->operands[operandIndex].type = typeFromString(typeName,
470 HasREX_WPrefix, OpSize);
471
472 ++operandIndex;
473 ++physicalOperandIndex;
474 }
475
emitInstructionSpecifier()476 void RecognizableInstr::emitInstructionSpecifier() {
477 Spec->name = Name;
478
479 Spec->insnContext = insnContext();
480
481 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
482
483 unsigned numOperands = OperandList.size();
484 unsigned numPhysicalOperands = 0;
485
486 // operandMapping maps from operands in OperandList to their originals.
487 // If operandMapping[i] != i, then the entry is a duplicate.
488 unsigned operandMapping[X86_MAX_OPERANDS];
489 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
490
491 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
492 if (OperandList[operandIndex].Constraints.size()) {
493 const CGIOperandList::ConstraintInfo &Constraint =
494 OperandList[operandIndex].Constraints[0];
495 if (Constraint.isTied()) {
496 operandMapping[operandIndex] = operandIndex;
497 operandMapping[Constraint.getTiedOperand()] = operandIndex;
498 } else {
499 ++numPhysicalOperands;
500 operandMapping[operandIndex] = operandIndex;
501 }
502 } else {
503 ++numPhysicalOperands;
504 operandMapping[operandIndex] = operandIndex;
505 }
506 }
507
508 #define HANDLE_OPERAND(class) \
509 handleOperand(false, \
510 operandIndex, \
511 physicalOperandIndex, \
512 numPhysicalOperands, \
513 operandMapping, \
514 class##EncodingFromString);
515
516 #define HANDLE_OPTIONAL(class) \
517 handleOperand(true, \
518 operandIndex, \
519 physicalOperandIndex, \
520 numPhysicalOperands, \
521 operandMapping, \
522 class##EncodingFromString);
523
524 // operandIndex should always be < numOperands
525 unsigned operandIndex = 0;
526 // physicalOperandIndex should always be < numPhysicalOperands
527 unsigned physicalOperandIndex = 0;
528
529 switch (Form) {
530 default: llvm_unreachable("Unhandled form");
531 case X86Local::RawFrmSrc:
532 HANDLE_OPERAND(relocation);
533 return;
534 case X86Local::RawFrmDst:
535 HANDLE_OPERAND(relocation);
536 return;
537 case X86Local::RawFrmDstSrc:
538 HANDLE_OPERAND(relocation);
539 HANDLE_OPERAND(relocation);
540 return;
541 case X86Local::RawFrm:
542 // Operand 1 (optional) is an address or immediate.
543 // Operand 2 (optional) is an immediate.
544 assert(numPhysicalOperands <= 2 &&
545 "Unexpected number of operands for RawFrm");
546 HANDLE_OPTIONAL(relocation)
547 HANDLE_OPTIONAL(immediate)
548 break;
549 case X86Local::RawFrmMemOffs:
550 // Operand 1 is an address.
551 HANDLE_OPERAND(relocation);
552 break;
553 case X86Local::AddRegFrm:
554 // Operand 1 is added to the opcode.
555 // Operand 2 (optional) is an address.
556 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
557 "Unexpected number of operands for AddRegFrm");
558 HANDLE_OPERAND(opcodeModifier)
559 HANDLE_OPTIONAL(relocation)
560 break;
561 case X86Local::MRMDestReg:
562 // Operand 1 is a register operand in the R/M field.
563 // Operand 2 is a register operand in the Reg/Opcode field.
564 // - In AVX, there is a register operand in the VEX.vvvv field here -
565 // Operand 3 (optional) is an immediate.
566 if (HasVEX_4V)
567 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
568 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
569 else
570 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
571 "Unexpected number of operands for MRMDestRegFrm");
572
573 HANDLE_OPERAND(rmRegister)
574
575 if (HasVEX_4V)
576 // FIXME: In AVX, the register below becomes the one encoded
577 // in ModRMVEX and the one above the one in the VEX.VVVV field
578 HANDLE_OPERAND(vvvvRegister)
579
580 HANDLE_OPERAND(roRegister)
581 HANDLE_OPTIONAL(immediate)
582 break;
583 case X86Local::MRMDestMem:
584 // Operand 1 is a memory operand (possibly SIB-extended)
585 // Operand 2 is a register operand in the Reg/Opcode field.
586 // - In AVX, there is a register operand in the VEX.vvvv field here -
587 // Operand 3 (optional) is an immediate.
588 if (HasVEX_4V)
589 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
590 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
591 else
592 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
593 "Unexpected number of operands for MRMDestMemFrm");
594 HANDLE_OPERAND(memory)
595
596 if (HasEVEX_K)
597 HANDLE_OPERAND(writemaskRegister)
598
599 if (HasVEX_4V)
600 // FIXME: In AVX, the register below becomes the one encoded
601 // in ModRMVEX and the one above the one in the VEX.VVVV field
602 HANDLE_OPERAND(vvvvRegister)
603
604 HANDLE_OPERAND(roRegister)
605 HANDLE_OPTIONAL(immediate)
606 break;
607 case X86Local::MRMSrcReg:
608 // Operand 1 is a register operand in the Reg/Opcode field.
609 // Operand 2 is a register operand in the R/M field.
610 // - In AVX, there is a register operand in the VEX.vvvv field here -
611 // Operand 3 (optional) is an immediate.
612 // Operand 4 (optional) is an immediate.
613
614 if (HasVEX_4V || HasVEX_4VOp3)
615 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
616 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
617 else
618 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
619 "Unexpected number of operands for MRMSrcRegFrm");
620
621 HANDLE_OPERAND(roRegister)
622
623 if (HasEVEX_K)
624 HANDLE_OPERAND(writemaskRegister)
625
626 if (HasVEX_4V)
627 // FIXME: In AVX, the register below becomes the one encoded
628 // in ModRMVEX and the one above the one in the VEX.VVVV field
629 HANDLE_OPERAND(vvvvRegister)
630
631 if (HasMemOp4Prefix)
632 HANDLE_OPERAND(immediate)
633
634 HANDLE_OPERAND(rmRegister)
635
636 if (HasVEX_4VOp3)
637 HANDLE_OPERAND(vvvvRegister)
638
639 if (!HasMemOp4Prefix)
640 HANDLE_OPTIONAL(immediate)
641 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
642 HANDLE_OPTIONAL(immediate)
643 break;
644 case X86Local::MRMSrcMem:
645 // Operand 1 is a register operand in the Reg/Opcode field.
646 // Operand 2 is a memory operand (possibly SIB-extended)
647 // - In AVX, there is a register operand in the VEX.vvvv field here -
648 // Operand 3 (optional) is an immediate.
649
650 if (HasVEX_4V || HasVEX_4VOp3)
651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
652 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
653 else
654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
655 "Unexpected number of operands for MRMSrcMemFrm");
656
657 HANDLE_OPERAND(roRegister)
658
659 if (HasEVEX_K)
660 HANDLE_OPERAND(writemaskRegister)
661
662 if (HasVEX_4V)
663 // FIXME: In AVX, the register below becomes the one encoded
664 // in ModRMVEX and the one above the one in the VEX.VVVV field
665 HANDLE_OPERAND(vvvvRegister)
666
667 if (HasMemOp4Prefix)
668 HANDLE_OPERAND(immediate)
669
670 HANDLE_OPERAND(memory)
671
672 if (HasVEX_4VOp3)
673 HANDLE_OPERAND(vvvvRegister)
674
675 if (!HasMemOp4Prefix)
676 HANDLE_OPTIONAL(immediate)
677 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
678 break;
679 case X86Local::MRMXr:
680 case X86Local::MRM0r:
681 case X86Local::MRM1r:
682 case X86Local::MRM2r:
683 case X86Local::MRM3r:
684 case X86Local::MRM4r:
685 case X86Local::MRM5r:
686 case X86Local::MRM6r:
687 case X86Local::MRM7r:
688 {
689 // Operand 1 is a register operand in the R/M field.
690 // Operand 2 (optional) is an immediate or relocation.
691 // Operand 3 (optional) is an immediate.
692 unsigned kOp = (HasEVEX_K) ? 1:0;
693 unsigned Op4v = (HasVEX_4V) ? 1:0;
694 if (numPhysicalOperands > 3 + kOp + Op4v)
695 llvm_unreachable("Unexpected number of operands for MRMnr");
696 }
697 if (HasVEX_4V)
698 HANDLE_OPERAND(vvvvRegister)
699
700 if (HasEVEX_K)
701 HANDLE_OPERAND(writemaskRegister)
702 HANDLE_OPTIONAL(rmRegister)
703 HANDLE_OPTIONAL(relocation)
704 HANDLE_OPTIONAL(immediate)
705 break;
706 case X86Local::MRMXm:
707 case X86Local::MRM0m:
708 case X86Local::MRM1m:
709 case X86Local::MRM2m:
710 case X86Local::MRM3m:
711 case X86Local::MRM4m:
712 case X86Local::MRM5m:
713 case X86Local::MRM6m:
714 case X86Local::MRM7m:
715 {
716 // Operand 1 is a memory operand (possibly SIB-extended)
717 // Operand 2 (optional) is an immediate or relocation.
718 unsigned kOp = (HasEVEX_K) ? 1:0;
719 unsigned Op4v = (HasVEX_4V) ? 1:0;
720 if (numPhysicalOperands < 1 + kOp + Op4v ||
721 numPhysicalOperands > 2 + kOp + Op4v)
722 llvm_unreachable("Unexpected number of operands for MRMnm");
723 }
724 if (HasVEX_4V)
725 HANDLE_OPERAND(vvvvRegister)
726 if (HasEVEX_K)
727 HANDLE_OPERAND(writemaskRegister)
728 HANDLE_OPERAND(memory)
729 HANDLE_OPTIONAL(relocation)
730 break;
731 case X86Local::RawFrmImm8:
732 // operand 1 is a 16-bit immediate
733 // operand 2 is an 8-bit immediate
734 assert(numPhysicalOperands == 2 &&
735 "Unexpected number of operands for X86Local::RawFrmImm8");
736 HANDLE_OPERAND(immediate)
737 HANDLE_OPERAND(immediate)
738 break;
739 case X86Local::RawFrmImm16:
740 // operand 1 is a 16-bit immediate
741 // operand 2 is a 16-bit immediate
742 HANDLE_OPERAND(immediate)
743 HANDLE_OPERAND(immediate)
744 break;
745 case X86Local::MRM_F8:
746 if (Opcode == 0xc6) {
747 assert(numPhysicalOperands == 1 &&
748 "Unexpected number of operands for X86Local::MRM_F8");
749 HANDLE_OPERAND(immediate)
750 } else if (Opcode == 0xc7) {
751 assert(numPhysicalOperands == 1 &&
752 "Unexpected number of operands for X86Local::MRM_F8");
753 HANDLE_OPERAND(relocation)
754 }
755 break;
756 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
757 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
758 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
759 case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4:
760 case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8:
761 case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB:
762 case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE:
763 case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1:
764 case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4:
765 case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9:
766 case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC:
767 case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0:
768 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3:
769 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6:
770 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA:
771 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD:
772 case X86Local::MRM_FE: case X86Local::MRM_FF:
773 // Ignored.
774 break;
775 }
776
777 #undef HANDLE_OPERAND
778 #undef HANDLE_OPTIONAL
779 }
780
emitDecodePath(DisassemblerTables & tables) const781 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
782 // Special cases where the LLVM tables are not complete
783
784 #define MAP(from, to) \
785 case X86Local::MRM_##from: \
786 filter = new ExactFilter(0x##from); \
787 break;
788
789 OpcodeType opcodeType = (OpcodeType)-1;
790
791 ModRMFilter* filter = nullptr;
792 uint8_t opcodeToSet = 0;
793
794 switch (OpMap) {
795 default: llvm_unreachable("Invalid map!");
796 case X86Local::OB:
797 case X86Local::TB:
798 case X86Local::T8:
799 case X86Local::TA:
800 case X86Local::XOP8:
801 case X86Local::XOP9:
802 case X86Local::XOPA:
803 switch (OpMap) {
804 default: llvm_unreachable("Unexpected map!");
805 case X86Local::OB: opcodeType = ONEBYTE; break;
806 case X86Local::TB: opcodeType = TWOBYTE; break;
807 case X86Local::T8: opcodeType = THREEBYTE_38; break;
808 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
809 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
810 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
811 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
812 }
813
814 switch (Form) {
815 default:
816 filter = new DumbFilter();
817 break;
818 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
819 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
820 case X86Local::MRMXr: case X86Local::MRMXm:
821 filter = new ModFilter(isRegFormat(Form));
822 break;
823 case X86Local::MRM0r: case X86Local::MRM1r:
824 case X86Local::MRM2r: case X86Local::MRM3r:
825 case X86Local::MRM4r: case X86Local::MRM5r:
826 case X86Local::MRM6r: case X86Local::MRM7r:
827 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
828 break;
829 case X86Local::MRM0m: case X86Local::MRM1m:
830 case X86Local::MRM2m: case X86Local::MRM3m:
831 case X86Local::MRM4m: case X86Local::MRM5m:
832 case X86Local::MRM6m: case X86Local::MRM7m:
833 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
834 break;
835 MRM_MAPPING
836 } // switch (Form)
837
838 opcodeToSet = Opcode;
839 break;
840 } // switch (OpMap)
841
842 assert(opcodeType != (OpcodeType)-1 &&
843 "Opcode type not set");
844 assert(filter && "Filter not set");
845
846 if (Form == X86Local::AddRegFrm) {
847 assert(((opcodeToSet & 7) == 0) &&
848 "ADDREG_FRM opcode not aligned");
849
850 uint8_t currentOpcode;
851
852 for (currentOpcode = opcodeToSet;
853 currentOpcode < opcodeToSet + 8;
854 ++currentOpcode)
855 tables.setTableFields(opcodeType,
856 insnContext(),
857 currentOpcode,
858 *filter,
859 UID, Is32Bit, IgnoresVEX_L);
860 } else {
861 tables.setTableFields(opcodeType,
862 insnContext(),
863 opcodeToSet,
864 *filter,
865 UID, Is32Bit, IgnoresVEX_L);
866 }
867
868 delete filter;
869
870 #undef MAP
871 }
872
873 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool hasREX_WPrefix,uint8_t OpSize)874 OperandType RecognizableInstr::typeFromString(const std::string &s,
875 bool hasREX_WPrefix,
876 uint8_t OpSize) {
877 if(hasREX_WPrefix) {
878 // For instructions with a REX_W prefix, a declared 32-bit register encoding
879 // is special.
880 TYPE("GR32", TYPE_R32)
881 }
882 if(OpSize == X86Local::OpSize16) {
883 // For OpSize16 instructions, a declared 16-bit register or
884 // immediate encoding is special.
885 TYPE("GR16", TYPE_Rv)
886 TYPE("i16imm", TYPE_IMMv)
887 } else if(OpSize == X86Local::OpSize32) {
888 // For OpSize32 instructions, a declared 32-bit register or
889 // immediate encoding is special.
890 TYPE("GR32", TYPE_Rv)
891 }
892 TYPE("i16mem", TYPE_Mv)
893 TYPE("i16imm", TYPE_IMM16)
894 TYPE("i16i8imm", TYPE_IMMv)
895 TYPE("GR16", TYPE_R16)
896 TYPE("i32mem", TYPE_Mv)
897 TYPE("i32imm", TYPE_IMMv)
898 TYPE("i32i8imm", TYPE_IMM32)
899 TYPE("u32u8imm", TYPE_IMM32)
900 TYPE("GR32", TYPE_R32)
901 TYPE("GR32orGR64", TYPE_R32)
902 TYPE("i64mem", TYPE_Mv)
903 TYPE("i64i32imm", TYPE_IMM64)
904 TYPE("i64i8imm", TYPE_IMM64)
905 TYPE("GR64", TYPE_R64)
906 TYPE("i8mem", TYPE_M8)
907 TYPE("i8imm", TYPE_IMM8)
908 TYPE("GR8", TYPE_R8)
909 TYPE("VR128", TYPE_XMM128)
910 TYPE("VR128X", TYPE_XMM128)
911 TYPE("f128mem", TYPE_M128)
912 TYPE("f256mem", TYPE_M256)
913 TYPE("f512mem", TYPE_M512)
914 TYPE("FR64", TYPE_XMM64)
915 TYPE("FR64X", TYPE_XMM64)
916 TYPE("f64mem", TYPE_M64FP)
917 TYPE("sdmem", TYPE_M64FP)
918 TYPE("FR32", TYPE_XMM32)
919 TYPE("FR32X", TYPE_XMM32)
920 TYPE("f32mem", TYPE_M32FP)
921 TYPE("ssmem", TYPE_M32FP)
922 TYPE("RST", TYPE_ST)
923 TYPE("i128mem", TYPE_M128)
924 TYPE("i256mem", TYPE_M256)
925 TYPE("i512mem", TYPE_M512)
926 TYPE("i64i32imm_pcrel", TYPE_REL64)
927 TYPE("i16imm_pcrel", TYPE_REL16)
928 TYPE("i32imm_pcrel", TYPE_REL32)
929 TYPE("SSECC", TYPE_IMM3)
930 TYPE("AVXCC", TYPE_IMM5)
931 TYPE("AVX512RC", TYPE_IMM32)
932 TYPE("brtarget", TYPE_RELv)
933 TYPE("uncondbrtarget", TYPE_RELv)
934 TYPE("brtarget8", TYPE_REL8)
935 TYPE("f80mem", TYPE_M80FP)
936 TYPE("lea32mem", TYPE_LEA)
937 TYPE("lea64_32mem", TYPE_LEA)
938 TYPE("lea64mem", TYPE_LEA)
939 TYPE("VR64", TYPE_MM64)
940 TYPE("i64imm", TYPE_IMMv)
941 TYPE("opaque32mem", TYPE_M1616)
942 TYPE("opaque48mem", TYPE_M1632)
943 TYPE("opaque80mem", TYPE_M1664)
944 TYPE("opaque512mem", TYPE_M512)
945 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
946 TYPE("DEBUG_REG", TYPE_DEBUGREG)
947 TYPE("CONTROL_REG", TYPE_CONTROLREG)
948 TYPE("srcidx8", TYPE_SRCIDX8)
949 TYPE("srcidx16", TYPE_SRCIDX16)
950 TYPE("srcidx32", TYPE_SRCIDX32)
951 TYPE("srcidx64", TYPE_SRCIDX64)
952 TYPE("dstidx8", TYPE_DSTIDX8)
953 TYPE("dstidx16", TYPE_DSTIDX16)
954 TYPE("dstidx32", TYPE_DSTIDX32)
955 TYPE("dstidx64", TYPE_DSTIDX64)
956 TYPE("offset8", TYPE_MOFFS8)
957 TYPE("offset16", TYPE_MOFFS16)
958 TYPE("offset32", TYPE_MOFFS32)
959 TYPE("offset64", TYPE_MOFFS64)
960 TYPE("VR256", TYPE_XMM256)
961 TYPE("VR256X", TYPE_XMM256)
962 TYPE("VR512", TYPE_XMM512)
963 TYPE("VK1", TYPE_VK1)
964 TYPE("VK1WM", TYPE_VK1)
965 TYPE("VK8", TYPE_VK8)
966 TYPE("VK8WM", TYPE_VK8)
967 TYPE("VK16", TYPE_VK16)
968 TYPE("VK16WM", TYPE_VK16)
969 TYPE("GR16_NOAX", TYPE_Rv)
970 TYPE("GR32_NOAX", TYPE_Rv)
971 TYPE("GR64_NOAX", TYPE_R64)
972 TYPE("vx32mem", TYPE_M32)
973 TYPE("vy32mem", TYPE_M32)
974 TYPE("vz32mem", TYPE_M32)
975 TYPE("vx64mem", TYPE_M64)
976 TYPE("vy64mem", TYPE_M64)
977 TYPE("vy64xmem", TYPE_M64)
978 TYPE("vz64mem", TYPE_M64)
979 errs() << "Unhandled type string " << s << "\n";
980 llvm_unreachable("Unhandled type string");
981 }
982 #undef TYPE
983
984 #define ENCODING(str, encoding) if (s == str) return encoding;
985 OperandEncoding
immediateEncodingFromString(const std::string & s,uint8_t OpSize)986 RecognizableInstr::immediateEncodingFromString(const std::string &s,
987 uint8_t OpSize) {
988 if(OpSize != X86Local::OpSize16) {
989 // For instructions without an OpSize prefix, a declared 16-bit register or
990 // immediate encoding is special.
991 ENCODING("i16imm", ENCODING_IW)
992 }
993 ENCODING("i32i8imm", ENCODING_IB)
994 ENCODING("u32u8imm", ENCODING_IB)
995 ENCODING("SSECC", ENCODING_IB)
996 ENCODING("AVXCC", ENCODING_IB)
997 ENCODING("AVX512RC", ENCODING_IB)
998 ENCODING("i16imm", ENCODING_Iv)
999 ENCODING("i16i8imm", ENCODING_IB)
1000 ENCODING("i32imm", ENCODING_Iv)
1001 ENCODING("i64i32imm", ENCODING_ID)
1002 ENCODING("i64i8imm", ENCODING_IB)
1003 ENCODING("i8imm", ENCODING_IB)
1004 // This is not a typo. Instructions like BLENDVPD put
1005 // register IDs in 8-bit immediates nowadays.
1006 ENCODING("FR32", ENCODING_IB)
1007 ENCODING("FR64", ENCODING_IB)
1008 ENCODING("VR128", ENCODING_IB)
1009 ENCODING("VR256", ENCODING_IB)
1010 ENCODING("FR32X", ENCODING_IB)
1011 ENCODING("FR64X", ENCODING_IB)
1012 ENCODING("VR128X", ENCODING_IB)
1013 ENCODING("VR256X", ENCODING_IB)
1014 ENCODING("VR512", ENCODING_IB)
1015 errs() << "Unhandled immediate encoding " << s << "\n";
1016 llvm_unreachable("Unhandled immediate encoding");
1017 }
1018
1019 OperandEncoding
rmRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1020 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1021 uint8_t OpSize) {
1022 ENCODING("RST", ENCODING_FP)
1023 ENCODING("GR16", ENCODING_RM)
1024 ENCODING("GR32", ENCODING_RM)
1025 ENCODING("GR32orGR64", ENCODING_RM)
1026 ENCODING("GR64", ENCODING_RM)
1027 ENCODING("GR8", ENCODING_RM)
1028 ENCODING("VR128", ENCODING_RM)
1029 ENCODING("VR128X", ENCODING_RM)
1030 ENCODING("FR64", ENCODING_RM)
1031 ENCODING("FR32", ENCODING_RM)
1032 ENCODING("FR64X", ENCODING_RM)
1033 ENCODING("FR32X", ENCODING_RM)
1034 ENCODING("VR64", ENCODING_RM)
1035 ENCODING("VR256", ENCODING_RM)
1036 ENCODING("VR256X", ENCODING_RM)
1037 ENCODING("VR512", ENCODING_RM)
1038 ENCODING("VK1", ENCODING_RM)
1039 ENCODING("VK8", ENCODING_RM)
1040 ENCODING("VK16", ENCODING_RM)
1041 errs() << "Unhandled R/M register encoding " << s << "\n";
1042 llvm_unreachable("Unhandled R/M register encoding");
1043 }
1044
1045 OperandEncoding
roRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1046 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1047 uint8_t OpSize) {
1048 ENCODING("GR16", ENCODING_REG)
1049 ENCODING("GR32", ENCODING_REG)
1050 ENCODING("GR32orGR64", ENCODING_REG)
1051 ENCODING("GR64", ENCODING_REG)
1052 ENCODING("GR8", ENCODING_REG)
1053 ENCODING("VR128", ENCODING_REG)
1054 ENCODING("FR64", ENCODING_REG)
1055 ENCODING("FR32", ENCODING_REG)
1056 ENCODING("VR64", ENCODING_REG)
1057 ENCODING("SEGMENT_REG", ENCODING_REG)
1058 ENCODING("DEBUG_REG", ENCODING_REG)
1059 ENCODING("CONTROL_REG", ENCODING_REG)
1060 ENCODING("VR256", ENCODING_REG)
1061 ENCODING("VR256X", ENCODING_REG)
1062 ENCODING("VR128X", ENCODING_REG)
1063 ENCODING("FR64X", ENCODING_REG)
1064 ENCODING("FR32X", ENCODING_REG)
1065 ENCODING("VR512", ENCODING_REG)
1066 ENCODING("VK1", ENCODING_REG)
1067 ENCODING("VK8", ENCODING_REG)
1068 ENCODING("VK16", ENCODING_REG)
1069 ENCODING("VK1WM", ENCODING_REG)
1070 ENCODING("VK8WM", ENCODING_REG)
1071 ENCODING("VK16WM", ENCODING_REG)
1072 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1073 llvm_unreachable("Unhandled reg/opcode register encoding");
1074 }
1075
1076 OperandEncoding
vvvvRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1077 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1078 uint8_t OpSize) {
1079 ENCODING("GR32", ENCODING_VVVV)
1080 ENCODING("GR64", ENCODING_VVVV)
1081 ENCODING("FR32", ENCODING_VVVV)
1082 ENCODING("FR64", ENCODING_VVVV)
1083 ENCODING("VR128", ENCODING_VVVV)
1084 ENCODING("VR256", ENCODING_VVVV)
1085 ENCODING("FR32X", ENCODING_VVVV)
1086 ENCODING("FR64X", ENCODING_VVVV)
1087 ENCODING("VR128X", ENCODING_VVVV)
1088 ENCODING("VR256X", ENCODING_VVVV)
1089 ENCODING("VR512", ENCODING_VVVV)
1090 ENCODING("VK1", ENCODING_VVVV)
1091 ENCODING("VK8", ENCODING_VVVV)
1092 ENCODING("VK16", ENCODING_VVVV)
1093 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1094 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1095 }
1096
1097 OperandEncoding
writemaskRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1098 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1099 uint8_t OpSize) {
1100 ENCODING("VK1WM", ENCODING_WRITEMASK)
1101 ENCODING("VK8WM", ENCODING_WRITEMASK)
1102 ENCODING("VK16WM", ENCODING_WRITEMASK)
1103 errs() << "Unhandled mask register encoding " << s << "\n";
1104 llvm_unreachable("Unhandled mask register encoding");
1105 }
1106
1107 OperandEncoding
memoryEncodingFromString(const std::string & s,uint8_t OpSize)1108 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1109 uint8_t OpSize) {
1110 ENCODING("i16mem", ENCODING_RM)
1111 ENCODING("i32mem", ENCODING_RM)
1112 ENCODING("i64mem", ENCODING_RM)
1113 ENCODING("i8mem", ENCODING_RM)
1114 ENCODING("ssmem", ENCODING_RM)
1115 ENCODING("sdmem", ENCODING_RM)
1116 ENCODING("f128mem", ENCODING_RM)
1117 ENCODING("f256mem", ENCODING_RM)
1118 ENCODING("f512mem", ENCODING_RM)
1119 ENCODING("f64mem", ENCODING_RM)
1120 ENCODING("f32mem", ENCODING_RM)
1121 ENCODING("i128mem", ENCODING_RM)
1122 ENCODING("i256mem", ENCODING_RM)
1123 ENCODING("i512mem", ENCODING_RM)
1124 ENCODING("f80mem", ENCODING_RM)
1125 ENCODING("lea32mem", ENCODING_RM)
1126 ENCODING("lea64_32mem", ENCODING_RM)
1127 ENCODING("lea64mem", ENCODING_RM)
1128 ENCODING("opaque32mem", ENCODING_RM)
1129 ENCODING("opaque48mem", ENCODING_RM)
1130 ENCODING("opaque80mem", ENCODING_RM)
1131 ENCODING("opaque512mem", ENCODING_RM)
1132 ENCODING("vx32mem", ENCODING_RM)
1133 ENCODING("vy32mem", ENCODING_RM)
1134 ENCODING("vz32mem", ENCODING_RM)
1135 ENCODING("vx64mem", ENCODING_RM)
1136 ENCODING("vy64mem", ENCODING_RM)
1137 ENCODING("vy64xmem", ENCODING_RM)
1138 ENCODING("vz64mem", ENCODING_RM)
1139 errs() << "Unhandled memory encoding " << s << "\n";
1140 llvm_unreachable("Unhandled memory encoding");
1141 }
1142
1143 OperandEncoding
relocationEncodingFromString(const std::string & s,uint8_t OpSize)1144 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1145 uint8_t OpSize) {
1146 if(OpSize != X86Local::OpSize16) {
1147 // For instructions without an OpSize prefix, a declared 16-bit register or
1148 // immediate encoding is special.
1149 ENCODING("i16imm", ENCODING_IW)
1150 }
1151 ENCODING("i16imm", ENCODING_Iv)
1152 ENCODING("i16i8imm", ENCODING_IB)
1153 ENCODING("i32imm", ENCODING_Iv)
1154 ENCODING("i32i8imm", ENCODING_IB)
1155 ENCODING("i64i32imm", ENCODING_ID)
1156 ENCODING("i64i8imm", ENCODING_IB)
1157 ENCODING("i8imm", ENCODING_IB)
1158 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1159 ENCODING("i16imm_pcrel", ENCODING_IW)
1160 ENCODING("i32imm_pcrel", ENCODING_ID)
1161 ENCODING("brtarget", ENCODING_Iv)
1162 ENCODING("brtarget8", ENCODING_IB)
1163 ENCODING("i64imm", ENCODING_IO)
1164 ENCODING("offset8", ENCODING_Ia)
1165 ENCODING("offset16", ENCODING_Ia)
1166 ENCODING("offset32", ENCODING_Ia)
1167 ENCODING("offset64", ENCODING_Ia)
1168 ENCODING("srcidx8", ENCODING_SI)
1169 ENCODING("srcidx16", ENCODING_SI)
1170 ENCODING("srcidx32", ENCODING_SI)
1171 ENCODING("srcidx64", ENCODING_SI)
1172 ENCODING("dstidx8", ENCODING_DI)
1173 ENCODING("dstidx16", ENCODING_DI)
1174 ENCODING("dstidx32", ENCODING_DI)
1175 ENCODING("dstidx64", ENCODING_DI)
1176 errs() << "Unhandled relocation encoding " << s << "\n";
1177 llvm_unreachable("Unhandled relocation encoding");
1178 }
1179
1180 OperandEncoding
opcodeModifierEncodingFromString(const std::string & s,uint8_t OpSize)1181 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1182 uint8_t OpSize) {
1183 ENCODING("GR32", ENCODING_Rv)
1184 ENCODING("GR64", ENCODING_RO)
1185 ENCODING("GR16", ENCODING_Rv)
1186 ENCODING("GR8", ENCODING_RB)
1187 ENCODING("GR16_NOAX", ENCODING_Rv)
1188 ENCODING("GR32_NOAX", ENCODING_Rv)
1189 ENCODING("GR64_NOAX", ENCODING_RO)
1190 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1191 llvm_unreachable("Unhandled opcode modifier encoding");
1192 }
1193 #undef ENCODING
1194