| /art/compiler/dex/quick/x86/ |
| D | fp_x86.cc | 155 AnnotateDalvikRegAccess(fild64, (src_v_reg_offset + LOWORD_OFFSET) >> 2, in GenLongToFP()
162 AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double); in GenLongToFP()
388 AnnotateDalvikRegAccess(fld_2, (src2_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
393 AnnotateDalvikRegAccess(fld_1, (src1_v_reg_offset + LOWORD_OFFSET) >> 2, in GenRemFP()
421 AnnotateDalvikRegAccess(fst, displacement >> 2, false /* is_load */, is_double /* is64bit */); in GenRemFP()
631 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); in GenInlinedAbsFloat()
632 AnnotateDalvikRegAccess(lir, displacement >> 2, true /* is_load */, false /* is_64bit*/); in GenInlinedAbsFloat()
695 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, true /* is_load */, true /* is_6… in GenInlinedAbsDouble()
696 …AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, false /*is_load */, true /* is_6… in GenInlinedAbsDouble()
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| D | int_x86.cc | 992 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
999 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedCas()
1290 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); in GenImulMemImm()
1431 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLongConst()
1514 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1536 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1547 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1569 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLong()
1617 AnnotateDalvikRegAccess(lir, (displacement + LOWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
1622 AnnotateDalvikRegAccess(lir, (displacement + HIWORD_OFFSET) >> 2, in GenLongRegOrMemOp()
[all …]
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| D | utility_x86.cc | 387 AnnotateDalvikRegAccess(l, offset >> 2, true /* is_load */, false /* is_64bit */); in OpRegMem()
414 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
415 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
440 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpRegMem()
707 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseIndexedDisp()
710 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, in LoadBaseIndexedDisp()
842 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in StoreBaseIndexedDisp()
845 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, in StoreBaseIndexedDisp()
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| D | target_x86.cc | 921 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, in GenConstWide()
924 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, in GenConstWide()
1365 AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); in GenInlinedIndexOf()
2270 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); in GenReduceVector()
2271 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); in GenReduceVector()
2712 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); in GenDalvikArgsRange()
2713 … AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); in GenDalvikArgsRange()
2722 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); in GenDalvikArgsRange()
2723 … AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); in GenDalvikArgsRange()
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| /art/compiler/dex/quick/mips/ |
| D | utility_mips.cc | 542 AnnotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in LoadBaseDispBody()
545 AnnotateDalvikRegAccess(load2, (displacement + HIWORD_OFFSET) >> 2, in LoadBaseDispBody()
644 AnnotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0)) >> 2, in StoreBaseDispBody()
647 AnnotateDalvikRegAccess(store2, (displacement + HIWORD_OFFSET) >> 2, in StoreBaseDispBody()
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| /art/compiler/dex/quick/ |
| D | gen_invoke.cc | 1043 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); in GenDalvikArgsRange()
1044 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, in GenDalvikArgsRange()
1054 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); in GenDalvikArgsRange()
1055 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, in GenDalvikArgsRange()
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| D | codegen_util.cc | 171 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, in AnnotateDalvikRegAccess() function in art::Mir2Lir
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| D | mir_to_lir.h | 668 void AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load, bool is64bit);
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| /art/compiler/dex/quick/arm/ |
| D | utility_arm.cc | 960 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
1082 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); in StoreBaseDispBody()
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| /art/compiler/dex/quick/arm64/ |
| D | utility_arm64.cc | 1269 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
1360 AnnotateDalvikRegAccess(store, displacement >> 2, false /* is_load */, r_src.Is64Bit()); in StoreBaseDispBody()
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