Searched refs:R10 (Results 1 – 8 of 8) sorted by relevance
| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64_test.cc | 56 registers_.push_back(new x86_64::CpuRegister(x86_64::R10)); in SetUpHelpers()
188 registers.push_back(new x86_64::CpuRegister(x86_64::R10)); in setcc_test_fn()
206 byte_regs[x86_64::R10] = "r10b"; in setcc_test_fn()
242 spill_regs.push_back(ManagedFromCpu(x86_64::R10)); in buildframe_test_fn()
286 spill_regs.push_back(ManagedFromCpu(x86_64::R10)); in removeframe_test_fn()
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| /art/runtime/arch/x86_64/ |
| D | registers_x86_64.h | 40 R10 = 10, enumerator
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| D | context_x86_64.cc | 79 gprs_[R10] = nullptr; in SmashCallerSaves()
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 129 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R10)); in ArmJniCallingConvention()
136 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 37 R10 = 10, enumerator
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| D | quick_method_frame_info_arm.h | 30 (1 << art::arm::R10) | (1 << art::arm::R11);
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| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 956 __ mul(R8, R9, R10); in TEST()
965 __ umull(R8, R9, R10, R11); in TEST()
979 __ sdiv(R8, R9, R10); in TEST()
982 __ udiv(R8, R9, R10); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_arm.cc | 254 blocked_registers[R10] = true; in SetupBlockedRegisters()
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