Searched refs:R12 (Results 1 – 10 of 10) sorted by relevance
| /art/runtime/arch/x86_64/ |
| D | registers_x86_64.h | 42 R12 = 12, enumerator
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| D | quick_method_frame_info_x86_64.h | 28 (1 << art::x86_64::RBX) | (1 << art::x86_64::RBP) | (1 << art::x86_64::R12) |
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 39 R12 = 12, enumerator
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| /art/compiler/jni/quick/x86_64/ |
| D | calling_convention_x86_64.cc | 129 callee_save_regs_.push_back(X86_64ManagedRegister::FromCpuRegister(R12)); in X86_64JniCallingConvention()
140 return 1 << RBX | 1 << RBP | 1 << R12 | 1 << R13 | 1 << R14 | 1 << R15 | in CoreSpillMask()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64_test.cc | 58 registers_.push_back(new x86_64::CpuRegister(x86_64::R12)); in SetUpHelpers()
190 registers.push_back(new x86_64::CpuRegister(x86_64::R12)); in setcc_test_fn()
208 byte_regs[x86_64::R12] = "r12b"; in setcc_test_fn()
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| /art/compiler/utils/arm/ |
| D | assembler_arm.cc | 833 __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value()); in Emit()
834 __ blx(R12); in Emit()
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| D | assembler_arm32.cc | 1471 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12); in MemoryBarrier()
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| D | assembler_thumb2.cc | 2521 CHECK_EQ(mscratch.AsArm().AsCoreRegister(), R12); in MemoryBarrier()
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| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 316 __ add(R12, R1, ShifterOperand(R0)); in TEST()
874 __ StoreToOffset(kStoreWord, R0, R12, 12); in TEST()
875 __ StoreToOffset(kStoreHalfword, R0, R12, 12); in TEST()
876 __ StoreToOffset(kStoreByte, R2, R12, 12); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.cc | 200 blocked_registers[R12] = true; in SetupBlockedRegisters()
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