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Searched refs:reg (Results 1 – 25 of 121) sorted by relevance

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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(EAX, reg.AsCpuRegister()); in TEST()
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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(RAX, reg.AsCpuRegister()); in TEST()
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/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCoreRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(R0, reg.AsCoreRegister()); in TEST()
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/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
33 Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); in TEST() local
35 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
36 EXPECT_TRUE(reg.IsCoreRegister()); in TEST()
37 EXPECT_TRUE(!reg.IsWRegister()); in TEST()
38 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
39 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
40 EXPECT_TRUE(reg.Overlaps(wreg)); in TEST()
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/art/compiler/dex/quick/
Dralloc_util.cc85 for (const RegStorage& reg : core_regs) { in RegisterPool() local
86 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool()
87 m2l_->reginfo_map_.Put(reg.GetReg(), info); in RegisterPool()
90 for (const RegStorage& reg : core64_regs) { in RegisterPool() local
91 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool()
92 m2l_->reginfo_map_.Put(reg.GetReg(), info); in RegisterPool()
95 for (const RegStorage& reg : sp_regs) { in RegisterPool() local
96 RegisterInfo* info = new (arena) RegisterInfo(reg, m2l_->GetRegMaskCommon(reg)); in RegisterPool()
97 m2l_->reginfo_map_.Put(reg.GetReg(), info); in RegisterPool()
100 for (const RegStorage& reg : dp_regs) { in RegisterPool() local
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Dgen_loadstore.cc86 OpRegCopy(r_dest, rl_src.reg); in LoadValueDirect()
122 OpRegCopyWide(r_dest, rl_src.reg); in LoadValueDirectWide()
148 if (!RegClassMatches(op_kind, rl_src.reg)) { in LoadValue()
151 OpRegCopy(new_reg, rl_src.reg); in LoadValue()
153 Clobber(rl_src.reg); in LoadValue()
155 rl_src.reg = new_reg; in LoadValue()
162 rl_src.reg = AllocTypedTemp(rl_src.fp, op_kind); in LoadValue()
163 LoadValueDirect(rl_src, rl_src.reg); in LoadValue()
191 if (IsLive(rl_src.reg) || in StoreValue()
192 IsPromoted(rl_src.reg) || in StoreValue()
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Dgen_common.cc61 void Mir2Lir::GenDivZeroCheck(RegStorage reg) { in GenDivZeroCheck() argument
62 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); in GenDivZeroCheck()
138 LIR* Mir2Lir::GenNullCheck(RegStorage reg) { in GenNullCheck() argument
153 LIR* branch = OpCmpImmBranch(kCondEq, reg, 0, nullptr); in GenNullCheck()
203 void Mir2Lir::ForceImplicitNullCheck(RegStorage reg, int opt_flags) { in ForceImplicitNullCheck() argument
212 LIR* load = Load32Disp(reg, 0, tmp); in ForceImplicitNullCheck()
265 OpCmpImmBranch(cond, rl_src1.reg, mir_graph_->ConstantValue(rl_src2), taken); in GenCompareAndBranch()
275 OpCmpImmBranch(cond, rl_src1.reg, 0, taken); in GenCompareAndBranch()
281 OpCmpBranch(cond, rl_src1.reg, rl_src2.reg, taken); in GenCompareAndBranch()
312 OpCmpImmBranch(cond, rl_src.reg, 0, taken); in GenCompareZeroAndBranch()
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/art/compiler/dex/quick/arm/
Dint_arm.cc129 OpRegReg(kOpCmp, rl_src1.reg.GetHigh(), rl_src2.reg.GetHigh()); in GenCmpLong()
132 OpRegRegReg(kOpSub, t_reg, rl_src1.reg.GetLow(), rl_src2.reg.GetLow()); in GenCmpLong()
146 rl_temp.reg.SetReg(t_reg.GetReg()); in GenCmpLong()
164 RegStorage low_reg = rl_src1.reg.GetLow(); in GenFusedLongCmpImmBranch()
165 RegStorage high_reg = rl_src1.reg.GetHigh(); in GenFusedLongCmpImmBranch()
251 OpRegRegImm(kOpSub, rl_result.reg, rl_src.reg, -true_val); in GenSelect()
254 LoadConstant(rl_result.reg, false_val); in GenSelect()
257 OpRegRegImm(kOpRsub, rl_result.reg, rl_src.reg, 1); in GenSelect()
260 LoadConstant(rl_result.reg, false_val); in GenSelect()
263 OpRegImm(kOpCmp, rl_src.reg, 0); in GenSelect()
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Dfp_arm.cc65 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
112 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpDouble()
142 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion()
152 NewLIR2(kThumb2VcvtF64U32, rl_result.reg.GetReg(), src_low.GetReg()); in GenConversion()
154 NewLIR3(kThumb2VmlaF64, rl_result.reg.GetReg(), tmp1.GetReg(), tmp2.GetReg()); in GenConversion()
165 RegisterInfo* info = GetRegInfo(rl_src.reg); in GenConversion()
181 NewLIR2(kThumb2VcvtDF, rl_result.reg.GetReg(), low_val.GetReg()); in GenConversion()
198 src_reg = rl_src.reg.GetReg(); in GenConversion()
201 src_reg = rl_src.reg.GetReg(); in GenConversion()
205 NewLIR2(op, rl_result.reg.GetReg(), src_reg); in GenConversion()
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/art/compiler/dex/quick/x86/
Dfp_x86.cc63 RegStorage r_dest = rl_result.reg; in GenArithOpFloat()
64 RegStorage r_src1 = rl_src1.reg; in GenArithOpFloat()
65 RegStorage r_src2 = rl_src2.reg; in GenArithOpFloat()
116 if (rl_result.reg == rl_src2.reg) { in GenArithOpDouble()
117 rl_src2.reg = AllocTempDouble(); in GenArithOpDouble()
118 OpRegCopy(rl_src2.reg, rl_result.reg); in GenArithOpDouble()
120 OpRegCopy(rl_result.reg, rl_src1.reg); in GenArithOpDouble()
121 NewLIR2(op, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpDouble()
138 RegisterInfo* reg_info = GetRegInfo(rl_src.reg); in GenLongToFP()
144 ResetDef(rl_src.reg); in GenLongToFP()
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Dint_x86.cc41 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); in GenCmpLong()
42 NewLIR2(kX86Set8R, rl_result.reg.GetReg(), kX86CondG); // result = (src1 > src2) ? 1 : 0 in GenCmpLong()
44 NewLIR2(kX86Sub8RR, rl_result.reg.GetReg(), temp_reg.GetReg()); in GenCmpLong()
45 NewLIR2(kX86Movsx8qRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); in GenCmpLong()
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch() argument
109 NewLIR2(reg.Is64Bit() ? kX86Test64RR: kX86Test32RR, reg.GetReg(), reg.GetReg()); in OpCmpImmBranch()
111 if (reg.Is64Bit()) { in OpCmpImmBranch()
112 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp64RI8 : kX86Cmp64RI, reg.GetReg(), check_value); in OpCmpImmBranch()
114 NewLIR2(IS_SIMM8(check_value) ? kX86Cmp32RI8 : kX86Cmp32RI, reg.GetReg(), check_value); in OpCmpImmBranch()
289 LoadConstantNoClobber(rl_result.reg, true_val); in GenSelect()
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/art/compiler/dex/quick/mips/
Dint_mips.cc51 NewLIR3(kMipsSlt, t0.GetReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); in GenCmpLong()
52 NewLIR3(kMipsSlt, t1.GetReg(), rl_src2.reg.GetHighReg(), rl_src1.reg.GetHighReg()); in GenCmpLong()
53 NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg()); in GenCmpLong()
54 LIR* branch = OpCmpImmBranch(kCondNe, rl_result.reg, 0, NULL); in GenCmpLong()
55 NewLIR3(kMipsSltu, t0.GetReg(), rl_src1.reg.GetLowReg(), rl_src2.reg.GetLowReg()); in GenCmpLong()
56 NewLIR3(kMipsSltu, t1.GetReg(), rl_src2.reg.GetLowReg(), rl_src1.reg.GetLowReg()); in GenCmpLong()
57 NewLIR3(kMipsSubu, rl_result.reg.GetReg(), t1.GetReg(), t0.GetReg()); in GenCmpLong()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch() argument
137 branch = OpCmpBranch(cond, reg, t_reg, target); in OpCmpImmBranch()
154 branch = OpCmpBranch(cond, reg, t_reg, target); in OpCmpImmBranch()
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/art/runtime/arch/arm64/
Dcontext_arm64.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress() argument
50 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
51 return gprs_[reg]; in GetGPRAddress()
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR() argument
55 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
56 if (gprs_[reg] == nullptr) { in GetGPR()
60 *val = *gprs_[reg]; in GetGPR()
65 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR() argument
68 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfDRegisters)); in GetFPR()
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/art/runtime/arch/x86_64/
Dcontext_x86_64.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress() argument
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
49 return gprs_[reg]; in GetGPRAddress()
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR() argument
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
54 if (gprs_[reg] == nullptr) { in GetGPR()
58 *val = *gprs_[reg]; in GetGPR()
63 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR() argument
66 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); in GetFPR()
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Dasm_support_x86_64.S80 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
81 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
82 #define CFI_RESTORE(reg) .cfi_restore reg argument
83 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
89 #define CFI_DEF_CFA(reg,size) argument
90 #define CFI_DEF_CFA_REGISTER(reg) argument
91 #define CFI_RESTORE(reg) argument
92 #define CFI_REL_OFFSET(reg,size) argument
148 MACRO1(PUSH, reg)
149 pushq REG_VAR(reg, 0)
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/art/test/404-optimizing-allocator/src/
DMain.java23 expectEquals(4, $opt$reg$TestLostCopy()); in main()
24 expectEquals(-10, $opt$reg$TestTwoLive()); in main()
25 expectEquals(-20, $opt$reg$TestThreeLive()); in main()
26 expectEquals(5, $opt$reg$TestFourLive()); in main()
27 expectEquals(10, $opt$reg$TestMultipleLive()); in main()
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); in main()
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); in main()
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); in main()
31 expectEquals(-77, $opt$reg$TestAgressiveLive2(1, 2, 3, 4, 5, 6, 7)); in main()
34 public static int $opt$reg$TestLostCopy() { in $opt$reg$TestLostCopy()
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/art/runtime/arch/arm/
Dcontext_arm.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress() argument
50 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
51 return gprs_[reg]; in GetGPRAddress()
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR() argument
55 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
56 if (gprs_[reg] == nullptr) { in GetGPR()
60 *val = *gprs_[reg]; in GetGPR()
65 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR() argument
68 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters)); in GetFPR()
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/art/runtime/arch/mips/
Dcontext_mips.h48 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress() argument
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
50 return gprs_[reg]; in GetGPRAddress()
53 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR() argument
54 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
55 if (gprs_[reg] == nullptr) { in GetGPR()
59 *val = *gprs_[reg]; in GetGPR()
64 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
66 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR() argument
67 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFRegisters)); in GetFPR()
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/art/compiler/dex/quick/arm64/
Dfp_arm64.cc62 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
115 NewLIR3(FWIDE(op), rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpDouble()
192 NewLIR2(op, rl_result.reg.GetReg(), rl_src.reg.GetReg()); in GenConversion()
211 NewLIR2(FWIDE(kA64Fcmp2ff), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenFusedFPCmpBranch()
217 NewLIR2(kA64Fcmp2ff, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenFusedFPCmpBranch()
283 LoadConstant(rl_result.reg, default_result); in GenCmpFP()
284 NewLIR2(FWIDE(kA64Fcmp2ff), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenCmpFP()
291 LoadConstant(rl_result.reg, default_result); in GenCmpFP()
292 NewLIR2(kA64Fcmp2ff, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenCmpFP()
294 DCHECK(!rl_result.reg.IsFloat()); in GenCmpFP()
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Dint_arm64.cc56 OpRegReg(kOpCmp, rl_src1.reg, rl_src2.reg); in GenCmpLong()
57 NewLIR4(kA64Csinc4rrrc, rl_result.reg.GetReg(), rwzr, rwzr, kArmCondEq); in GenCmpLong()
58 NewLIR4(kA64Csneg4rrrc, rl_result.reg.GetReg(), rl_result.reg.GetReg(), in GenCmpLong()
59 rl_result.reg.GetReg(), kArmCondGe); in GenCmpLong()
85 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg)); in GenShiftOpLong()
187 OpRegImm(kOpCmp, rl_src.reg, 0); in GenSelect()
194 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg, in GenSelect()
208 NewLIR4(opcode, rl_result.reg.GetReg(), in GenSelect()
209 rl_true.reg.GetReg(), rl_false.reg.GetReg(), ArmConditionEncoding(mir->meta.ccode)); in GenSelect()
234 OpCmpImmBranch(ccode, rl_src1.reg, 0, taken); in GenFusedLongCmpBranch()
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/art/runtime/arch/x86/
Dcontext_x86.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress() argument
48 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
49 return gprs_[reg]; in GetGPRAddress()
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR() argument
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
54 if (gprs_[reg] == nullptr) { in GetGPR()
58 *val = *gprs_[reg]; in GetGPR()
63 bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE;
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR() argument
70 bool SetFPR(uint32_t reg, uintptr_t value) OVERRIDE { in SetFPR() argument
Dasm_support_x86.S80 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
81 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
82 #define CFI_RESTORE(reg) .cfi_restore reg argument
83 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
91 #define CFI_DEF_CFA(reg,size) argument
92 #define CFI_DEF_CFA_REGISTER(reg) argument
93 #define CFI_RESTORE(reg) argument
94 #define CFI_REL_OFFSET(reg,size) argument
153 MACRO1(PUSH, reg)
154 pushl REG_VAR(reg, 0)
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/art/runtime/entrypoints/portable/
Dportable_thread_entrypoints.cc41 for (size_t reg = 0; reg < num_regs; ++reg) { in VisitFrame() local
42 if (TestBitmap(reg, reg_bitmap)) { in VisitFrame()
43 new_frame->SetVRegReference(reg, cur_frame->GetVRegReference(reg)); in VisitFrame()
45 new_frame->SetVReg(reg, cur_frame->GetVReg(reg)); in VisitFrame()
64 static bool TestBitmap(int reg, const uint8_t* reg_vector) { in TestBitmap() argument
65 return ((reg_vector[reg / 8] >> (reg % 8)) & 0x01) != 0; in TestBitmap()
/art/compiler/dex/
Dreg_storage.h107 constexpr RegStorage(RegStorageKind rs_kind, int reg) in RegStorage() argument
111 kValid | rs_kind | (reg & kRegTypeMask)) { in RegStorage()
183 static constexpr bool IsFloat(uint16_t reg) { in IsFloat() argument
184 return ((reg & kFloatingPoint) == kFloatingPoint); in IsFloat()
187 static constexpr bool IsDouble(uint16_t reg) { in IsDouble() argument
188 return (reg & (kFloatingPoint | k64BitMask)) == (kFloatingPoint | k64Bits); in IsDouble()
191 static constexpr bool IsSingle(uint16_t reg) { in IsSingle() argument
192 return (reg & (kFloatingPoint | k64BitMask)) == kFloatingPoint; in IsSingle()
195 static constexpr bool Is32Bit(uint16_t reg) { in Is32Bit() argument
196 return ((reg & kShapeMask) == k32BitSolo); in Is32Bit()
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/art/runtime/
Dquick_exception_handler.cc197 static VRegKind GetVRegKind(uint16_t reg, const std::vector<int32_t>& kinds) { in GetVRegKind() argument
198 return static_cast<VRegKind>(kinds.at(reg * 2)); in GetVRegKind()
219 for (uint16_t reg = 0; reg < num_regs; ++reg) { in HandleDeoptimization() local
220 VRegKind kind = GetVRegKind(reg, kinds); in HandleDeoptimization()
223 new_frame->SetVReg(reg, 0xEBADDE09); in HandleDeoptimization()
226 new_frame->SetVReg(reg, kinds.at((reg * 2) + 1)); in HandleDeoptimization()
229 new_frame->SetVRegReference(reg, in HandleDeoptimization()
231 reg, kind))); in HandleDeoptimization()
234 if (GetVRegKind(reg + 1, kinds) == kLongHiVReg) { in HandleDeoptimization()
236 new_frame->SetVRegLong(reg, GetVRegPair(h_method.Get(), reg, kLongLoVReg, kLongHiVReg)); in HandleDeoptimization()
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