Searched refs:rl_src_offset (Results 1 – 4 of 4) sorted by relevance
| /art/compiler/dex/quick/ |
| D | gen_invoke.cc | 1610 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedUnsafeGet() local
1611 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedUnsafeGet()
1615 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedUnsafeGet()
1655 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedUnsafePut() local
1656 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedUnsafePut()
1662 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedUnsafePut()
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 927 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
929 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedCas()
944 RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
967 const bool off_in_di = IsInReg(this, rl_src_offset, rs_rDI); in GenInlinedCas()
968 const bool off_in_si = IsInReg(this, rl_src_offset, rs_rSI); in GenInlinedCas()
995 LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); in GenInlinedCas()
1038 rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
1040 rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedCas()
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 800 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
801 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] in GenInlinedCas()
866 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); in GenInlinedCas()
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 709 RegLocation rl_src_offset = info->args[2]; // long low in GenInlinedCas() local
718 RegLocation rl_offset = LoadValueWide(rl_src_offset, kCoreReg); in GenInlinedCas()
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