Searched refs:ADR (Results 1 – 25 of 32) sorted by relevance
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64ExternalSymbolizer.cpp | 107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand() 116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
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/external/vixl/src/a64/ |
D | instructions-a64.cc | 189 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in SetPCRelImmTarget()
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D | constants-a64.h | 314 ADR = PCRelAddressingFixed | 0x00000000, enumerator
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D | disasm-a64.cc | 531 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; in VisitPCRelAddressing()
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D | simulator-a64.cc | 507 case ADR: in VisitPCRelAddressing()
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D | assembler-a64.cc | 535 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
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/external/chromium_org/v8/src/arm64/ |
D | instructions-arm64.h | 189 return Mask(PCRelAddressingMask) == ADR; in IsAdr()
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D | constants-arm64.h | 424 ADR = PCRelAddressingFixed | 0x00000000, enumerator
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D | disasm-arm64.cc | 524 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; in VisitPCRelAddressing()
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D | assembler-arm64.cc | 1075 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
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D | simulator-arm64.cc | 1279 case ADR: in VisitPCRelAddressing()
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/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb1.txt | 55 # ADR
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D | basic-arm-instructions.txt | 168 # ADR
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D | thumb2.txt | 91 # ADR
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/external/tremolo/Tremolo/ |
D | dpen.s | 63 ADR r14,dpen_read_return 458 ADR r6,.Lcrc_lookup
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D | mdctARM.s | 1003 ADR r6, bitrev 1033 ADR r7, .Lsincos_lookup @ sincos_lookup0 + 1127 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
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D | mdctLARM.s | 989 ADR r6, bitrev
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
D | AArch64MCCodeEmitter.cpp | 259 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
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/external/llvm/test/MC/ARM/ |
D | basic-thumb-instructions.s | 86 @ ADR
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/external/llvm/lib/Target/ARM/ |
D | ARMAsmPrinter.cpp | 1187 : ARM::ADR)) in EmitInstruction() 1204 : ARM::ADR)) in EmitInstruction()
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D | ARMInstrThumb.td | 116 // ADR instruction labels.
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D | ARMScheduleSwift.td | 1164 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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D | ARMInstrThumb2.td | 173 // ADR instruction labels. 4608 // ADR w/o the .w suffix
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/external/qemu-pc-bios/bochs/bios/ |
D | acpi-dsdt.hex | 89 0x41,0x44,0x52,0x0C,0x00,0x00,0x02,0x00, /* 00000250 "ADR....." */
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/external/llvm/lib/Target/AArch64/ |
D | AArch64SchedCyclone.td | 136 // ADR,ADRP
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