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Searched refs:CP0SRSC4_SRS13 (Results 1 – 2 of 2) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c303 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
Dcpu.h269 #define CP0SRSC4_SRS13 0 macro