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Searched refs:CP0_SRSConf0 (Results 1 – 5 of 5) sorted by relevance

/external/qemu/target-mips/
Dtranslate_init.c84 int32_t CP0_SRSConf0; member
290 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
Dmachine.c105 qemu_put_sbe32s(f, &env->CP0_SRSConf0); in cpu_save()
256 qemu_get_sbe32s(f, &env->CP0_SRSConf0); in cpu_load()
Dcpu.h242 int32_t CP0_SRSConf0; member
Dtranslate.c3078 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); in gen_mfc0()
4248 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0)); in gen_dmfc0()
8657 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; in cpu_reset()
Dop_helper.c1282 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; in helper_mtc0_srsconf0()