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Searched refs:CPUMIPSState (Results 1 – 7 of 7) sorted by relevance

/external/qemu/target-mips/
Dop_helper.c30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
33 static inline void compute_hflags(CPUMIPSState *env) in compute_hflags()
85 void helper_raise_exception_err (CPUMIPSState *env, in helper_raise_exception_err()
97 void helper_raise_exception (CPUMIPSState *env, uint32_t exception) in helper_raise_exception()
102 void helper_interrupt_restart (CPUMIPSState *env) in helper_interrupt_restart()
115 static void do_restore_state (CPUMIPSState *env, uintptr_t pc) in do_restore_state()
128 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
135 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
156 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ in HELPER_LD()
163 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
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Dcpu.h11 #define CPUOldState struct CPUMIPSState
13 #define CPUArchState struct CPUMIPSState
28 struct CPUMIPSState;
49 …int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, i…
50 void (*helper_tlbwi)(struct CPUMIPSState *env);
51 void (*helper_tlbwr)(struct CPUMIPSState *env);
52 void (*helper_tlbp)(struct CPUMIPSState *env);
53 void (*helper_tlbr)(struct CPUMIPSState *env);
180 typedef struct CPUMIPSState CPUMIPSState; typedef
181 struct CPUMIPSState { struct
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Dtranslate.c564 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); in gen_load_srsgpr()
587 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); in gen_store_srsgpr()
604 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_load_fpr32()
609 tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); in gen_store_fpr32()
614 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_load_fpr32h()
619 tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); in gen_store_fpr32h()
625 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d)); in gen_load_fpr64()
640 tcg_gen_st_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d)); in gen_store_fpr64()
780 static inline void restore_cpu_state (CPUMIPSState *env, DisasContext *ctx) in restore_cpu_state()
878 static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags) in check_insn()
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Dhelper.c37 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, in no_mmu_map_address()
46 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, in fixed_mmu_map_address()
64 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, in r4k_map_address()
107 static int get_physical_address (CPUMIPSState *env, hwaddr *physical, in get_physical_address()
209 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, in raise_mmu_exception()
271 static inline target_ulong cpu_mips_get_pgd(CPUMIPSState *env) in cpu_mips_get_pgd()
343 extern void r4k_helper_ptw_tlbrefill(CPUMIPSState*);
345 static inline int cpu_mips_tlb_refill(CPUMIPSState *env, target_ulong address, int rw , in cpu_mips_tlb_refill()
438 int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, in cpu_mips_handle_mmu_fault()
487 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) in cpu_mips_translate_address()
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Dcpu-qom.h10 CPUMIPSState env;
14 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) in mips_env_get_cpu()
Dtranslate_init.c474 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) in no_mmu_init()
480 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) in fixed_mmu_init()
486 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) in r4k_mmu_init()
496 static void mmu_init (CPUMIPSState *env, const mips_def_t *def) in mmu_init()
519 static void fpu_init (CPUMIPSState *env, const mips_def_t *def) in fpu_init()
529 static void mvp_init (CPUMIPSState *env, const mips_def_t *def) in mvp_init()
Dmachine.c45 CPUMIPSState *env = opaque; in cpu_save()
192 CPUMIPSState *env = opaque; in cpu_load()