| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 228 VQMOVUN.S16 D16,Q8
232 VZIP.8 D16,D17
252 VST1.32 D16,[R2]!
279 VQMOVUN.S16 D16,Q8
283 VZIP.8 D16,D17
303 VST1.32 D16,[R8]!
359 VQMOVUN.S16 D16,Q8
363 VZIP.8 D16,D17
383 VST1.32 D16,[R2]!
401 VQMOVUN.S16 D16,Q8
[all …]
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| /external/libhevc/common/arm/ |
| D | ihevc_sao_band_offset_chroma.s | 186 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
187 VORR.U8 D1,D1,D16 @band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
196 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
197 VAND.U8 D1,D1,D16 @band_table.val[0] = vand_u8(band_table.val[0], au1_cmp)
213 …VADD.I8 D16,D12,D30 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], band_p…
225 …VADD.I8 D12,D16,D26 @band_table_v.val[3] = vadd_u8(band_table_v.val[3], vdup_n…
299 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
307 …VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(…
353 VSUB.I8 D16,D14,D30 @vsub_u8(au1_cur_row_deint.val[1], band_pos_v)
361 …VTBX.8 D14,{D9-D12},D16 @vtbx4_u8(au1_cur_row_deint.val[1], band_table_v, vsub_u8(…
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| D | ihevc_sao_edge_offset_class0_chroma.s | 214 VTBL.8 D16,{D11},D14 @offset = vtbl1_s8(offset_tbl_u, vget_low_s8(edge_idx))
221 VZIP.S8 D16,D17
225 …VADDW.S8 Q9,Q9,D16 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0],…
379 VTBL.8 D16,{D11},D14 @offset = vtbl1_s8(offset_tbl_u, vget_low_s8(edge_idx))
386 VZIP.S8 D16,D17
388 …VADDW.S8 Q9,Q9,D16 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0],…
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| D | ihevc_sao_band_offset_luma.s | 203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
205 …VTBX.8 D15,{D1-D4},D16 @vtbx4_u8(au1_cur_row, band_table, vsub_u8(au1_cur_row, ba…
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| D | ihevc_sao_edge_offset_class2.s | 268 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
333 VLD1.8 D16,[r8]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
404 …VMOVL.U8 Q10,D16 @III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
447 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
580 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
710 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| D | ihevc_sao_edge_offset_class3.s | 279 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
349 VLD1.8 D16,[r8]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
441 …VMOVL.U8 Q10,D16 @III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
474 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
608 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
746 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| D | ihevc_sao_edge_offset_class3_chroma.s | 354 VLD1.8 D16,[r11]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
439 VLD1.8 D16,[r11]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
546 …VMOVL.U8 Q10,D16 @III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
593 VLD1.8 D16,[r11]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
747 VLD1.8 D16,[r9]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
912 VLD1.8 D16,[r9]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| D | ihevc_sao_edge_offset_class2_chroma.s | 358 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
443 VLD1.8 D16,[r8]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
562 …VMOVL.U8 Q10,D16 @III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
591 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
740 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
884 VLD1.8 D16,[r8]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
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| /external/llvm/test/CodeGen/ARM/ |
| D | subreg-remat.ll | 20 ; CHECK: vldr [[D16:d[0-9]+]],
21 ; CHECK: vstr [[D16]], [r1]
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| /external/llvm/test/MC/MachO/ |
| D | x86_64-symbols.s | 53 D16: label
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| D | x86_32-symbols.s | 53 D16: label
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| /external/llvm/test/TableGen/ |
| D | if.td | 44 def D16 : S<16>;
50 // CHECK: def D16
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| /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/ |
| D | armSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S | 96 #define dUr0 D16.F32
131 #define dVr1 D16.F32
148 #define dYr0 D16.F32
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| D | armSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S | 106 #define dUr0 D16.S32
142 #define dVr1 D16.S32
161 #define dYr0 D16.S32
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| D | armSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S | 107 #define dUr0 D16.S16
143 #define dVr1 D16.S16
164 #define dYr0 D16.S16
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| D | armSP_FFT_CToC_FC32_Radix4_fs_unsafe_s.S | 95 #define dZr0 D16.F32
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| D | armSP_FFTInv_CCSToR_F32_preTwiddleRadix2_unsafe_s.S | 107 #define qT2 D16.F32
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| D | armSP_FFT_CToC_SC16_Radix4_fs_unsafe_s.S | 95 #define dZr0 D16.S16
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| D | armSP_FFT_CToC_SC32_Radix4_fs_unsafe_s.S | 103 #define dZr0 D16.S32
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| D | armSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S | 88 #define dYr0 D16.F32
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 119 def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
148 def Q8 : ARMReg< 8, "q8", [D16, D17]>;
286 // Allocate non-VFP2 registers D16-D31 first.
329 // Allocate starting at non-VFP2 registers D16-D31 first.
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| D | ARMBaseRegisterInfo.cpp | 141 assert(ARM::D31 == ARM::D16 + 15); in getReservedRegs()
143 Reserved.set(ARM::D16 + i); in getReservedRegs()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 148 def D16 : SparcReg< 1, "F32">;
174 def Q8 : Rq< 1, "F32", [D16, D17]>;
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| D | SparcRegisterInfo.cpp | 81 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
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| /external/valgrind/main/memcheck/ |
| D | mc_machine.c | 918 if (o >= GOF(D16) && o+sz <= GOF(D16)+SZB(D16)) return GOF(D16); in get_otrack_shadow_offset_wrk()
946 if (o >= GOF(D16) && o+sz <= GOF(D16)+2*SZB(D16)) return GOF(D16); // Q8 in get_otrack_shadow_offset_wrk()
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