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/external/libhevc/common/arm/
Dihevc_sao_band_offset_chroma.s123 VLD1.8 D30,[r7] @pi1_sao_offset_u load
126 VDUP.8 D29,D30[1] @vdup_n_u8(pi1_sao_offset_u[1])
129 VDUP.8 D28,D30[2] @vdup_n_u8(pi1_sao_offset_u[2])
132 VDUP.8 D27,D30[3] @vdup_n_u8(pi1_sao_offset_u[3])
136 VDUP.8 D26,D30[4] @vdup_n_u8(pi1_sao_offset_u[4])
141 VMOV.I8 D30,#16 @vdup_n_u8(16)
157 VCLE.U8 D13,D4,D30 @vcle_u8(band_table.val[3], vdup_n_u8(16))
166 VCLE.U8 D14,D3,D30 @vcle_u8(band_table.val[2], vdup_n_u8(16))
176 VCLE.U8 D15,D2,D30 @vcle_u8(band_table.val[1], vdup_n_u8(16))
186 VCLE.U8 D16,D1,D30 @vcle_u8(band_table.val[0], vdup_n_u8(16))
[all …]
Dihevc_sao_edge_offset_class1.s130 VLD1.8 D30,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
148 VLD1.8 D30,[r6]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
212 VMOVN.I16 D30,Q13 @II vmovn_s16(pi2_tmp_cur_row.val[0])
248 VMOVN.I16 D30,Q13 @vmovn_s16(pi2_tmp_cur_row.val[0])
274 VLD1.8 D30,[r12] @vld1_u8(pu1_src[(ht - 1) * src_strd])
275 VST1.8 {D30},[r3] @vst1_u8(pu1_src_top[col])
290 VLD1.8 D30,[r6]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
331 VMOVN.I16 D30,Q13 @II vmovn_s16(pi2_tmp_cur_row.val[0])
334 VST1.8 {D30},[r10],r1 @II vst1q_u8(pu1_src_cpy, pu1_cur_row)
360 VMOVN.I16 D30,Q13 @vmovn_s16(pi2_tmp_cur_row.val[0])
[all …]
Dihevc_sao_band_offset_luma.s117 VLD1.8 D30,[r6] @pi1_sao_offset load
120 VDUP.8 D29,D30[1] @vdup_n_u8(pi1_sao_offset[1])
123 VDUP.8 D28,D30[2] @vdup_n_u8(pi1_sao_offset[2])
126 VDUP.8 D27,D30[3] @vdup_n_u8(pi1_sao_offset[3])
129 VDUP.8 D26,D30[4] @vdup_n_u8(pi1_sao_offset[4])
Dihevc_sao_edge_offset_class1_chroma.s135 VLD1.8 D30,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
153 VLD1.8 D30,[r6]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
225 VMOVN.I16 D30,Q13 @II vmovn_s16(pi2_tmp_cur_row.val[0])
266 VMOVN.I16 D30,Q13 @vmovn_s16(pi2_tmp_cur_row.val[0])
292 VLD1.8 D30,[r12] @vld1_u8(pu1_src[(ht - 1) * src_strd])
293 VST1.8 {D30},[r3] @vst1_u8(pu1_src_top[col])
308 VLD1.8 D30,[r6]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
362 VMOVN.I16 D30,Q13 @II vmovn_s16(pi2_tmp_cur_row.val[0])
365 VST1.8 {D30},[r10],r1 @II vst1q_u8(pu1_src_cpy, pu1_cur_row)
396 VMOVN.I16 D30,Q13 @vmovn_s16(pi2_tmp_cur_row.val[0])
[all …]
Dihevc_sao_edge_offset_class0_chroma.s156 VLD1.8 D30,[r12]! @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
245 …VMOVL.U8 Q14,D30 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u…
319 VLD1.8 D30,[r12]! @II pu1_cur_row = vld1q_u8(pu1_src_cpy)
384 …VMOVL.U8 Q12,D30 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u…
Dihevc_sao_edge_offset_class2_chroma.s400 VLD1.8 D30,[r2] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
409 VTBL.8 D18,{D30},D18 @I vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
412 VTBL.8 D19,{D30},D19 @I vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
446 VLD1.8 D30,[r11]! @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
613 VLD1.8 D30,[r2] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
633 VTBL.8 D26,{D30},D26 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
634 VTBL.8 D27,{D30},D27 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
Dihevc_sao_edge_offset_class0.s227 VTBL.8 D30,{D11},D28 @II offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
235 …VADDW.S8 Q0,Q0,D30 @II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[…
Dihevc_sao_edge_offset_class2.s339 VLD1.8 D30,[r11]! @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
757 VMOVN.I16 D30,Q14 @vmovn_s16(pi2_tmp_cur_row.val[0])
759 VST1.8 {D30},[r0],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
Dihevc_sao_edge_offset_class3.s355 VLD1.8 D30,[r2]! @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
805 VMOVN.I16 D30,Q14 @vmovn_s16(pi2_tmp_cur_row.val[0])
807 VST1.8 {D30},[r0],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
Dihevc_sao_edge_offset_class3_chroma.s449 VLD1.8 D30,[r4]! @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
999 VMOVN.I16 D30,Q14 @vmovn_s16(pi2_tmp_cur_row.val[0])
1001 VST1.8 {D30},[r0],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s166 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
218 VADDW.U8 Q7,Q4,D30 @//Q7 - HAS Y + B
219 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
220 VADDW.U8 Q9,Q6,D30 @//Q9 - HAS Y + G
269 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
349 VADDW.U8 Q7,Q4,D30 @//Q7 - HAS Y + B
350 VADDW.U8 Q8,Q5,D30 @//Q8 - HAS Y + R
351 VADDW.U8 Q9,Q6,D30 @//Q9 - HAS Y + G
/external/harfbuzz_ng/test/shaping/tests/
Dindic-pref-blocking.tests1 fonts/sha1sum/226bc2deab3846f1a682085f70c67d0421014144.ttf:U+0D2F,U+0D4D,U+0D30,U+0D46:[evowelsignm…
2 fonts/sha1sum/e207635780b42f898d58654b65098763e340f5c7.ttf:U+0D2F,U+0D4D,U+0D30,U+0D46:[yamlym=0+21…
/external/llvm/test/MC/MachO/
Dx86_64-symbols.s95 D30: label
Dx86_32-symbols.s95 D30: label
/external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/
DarmSP_FFT_CToC_FC32_Radix8_fs_unsafe_s.S111 #define dUr7 D30.F32
129 #define dVr6 D30.F32
162 #define dYr7 D30.F32
DarmSP_FFT_CToC_SC32_Radix8_fs_unsafe_s.S121 #define dUr7 D30.S32
140 #define dVr6 D30.S32
175 #define dYr7 D30.S32
DarmSP_FFT_CToC_SC16_Radix8_fs_unsafe_s.S122 #define dUr7 D30.S16
141 #define dVr6 D30.S16
179 #define dYr7 D30.S16
DarmSP_FFT_CToC_FC32_Radix4_ls_unsafe_s.S116 #define dZr3 D30.F32
DarmSP_FFT_CToC_SC32_Radix4_ls_unsafe_s.S124 #define dZr3 D30.S32
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td162 def D30 : SparcReg<29, "F60">;
181 def Q15 : Rq<29, "F60", [D30, D31]>;
/external/valgrind/main/memcheck/
Dmc_machine.c932 if (o >= GOF(D30) && o+sz <= GOF(D30)+SZB(D30)) return GOF(D30); in get_otrack_shadow_offset_wrk()
953 if (o >= GOF(D30) && o+sz <= GOF(D30)+2*SZB(D30)) return GOF(D30); // Q15 in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h141 case AArch64::D30: return AArch64::B30; in getBRegFromDReg()
181 case AArch64::B30: return AArch64::D30; in getDRegFromBReg()
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td133 def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
155 def Q15 : ARMReg<15, "q15", [D30, D31]>;
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp101 SP::D14, SP::D30, SP::D15, SP::D31 };
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td346 def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
381 def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;

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