Searched refs:DestRC (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg() local
42 if (DestRC != SrcRC) in copyPhysReg()
45 if (DestRC == &NVPTX::Int32RegsRegClass) in copyPhysReg()
48 else if (DestRC == &NVPTX::Int1RegsRegClass) in copyPhysReg()
51 else if (DestRC == &NVPTX::Float32RegsRegClass) in copyPhysReg()
54 else if (DestRC == &NVPTX::Int16RegsRegClass) in copyPhysReg()
57 else if (DestRC == &NVPTX::Int64RegsRegClass) in copyPhysReg()
60 else if (DestRC == &NVPTX::Float64RegsRegClass) in copyPhysReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 389 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
394 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
397 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
578 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in ListScheduleBottomUp() local
588 if (DestRC != RC) { in ListScheduleBottomUp()
590 if (!DestRC && !NewDef) in ListScheduleBottomUp()
597 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1138 const TargetRegisterClass *DestRC, in InsertCopiesAndMoveSuccs() argument
1143 CopyFromSU->CopyDstRC = DestRC; in InsertCopiesAndMoveSuccs()
1146 CopyToSU->CopySrcRC = DestRC; in InsertCopiesAndMoveSuccs()
1445 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); in PickNodeToScheduleBottomUp() local
1455 if (DestRC != RC) { in PickNodeToScheduleBottomUp()
1457 if (!DestRC && !NewDef) in PickNodeToScheduleBottomUp()
1463 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies); in PickNodeToScheduleBottomUp()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.cpp | 1389 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitUnaryOp() local
1390 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
1392 unsigned DestSub0 = MRI.createVirtualRegister(DestRC); in splitScalar64BitUnaryOp()
1403 unsigned FullDestReg = MRI.createVirtualRegister(DestRC); in splitScalar64BitUnaryOp()
1449 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg()); in splitScalar64BitBinaryOp() local
1450 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
1452 unsigned DestSub0 = MRI.createVirtualRegister(DestRC); in splitScalar64BitBinaryOp()
1467 unsigned FullDestReg = MRI.createVirtualRegister(DestRC); in splitScalar64BitBinaryOp()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrAVX512.td | 370 RegisterClass DestRC,
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
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