| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZShortenInst.cpp | 80 unsigned GPRs = GPRMap[Reg]; in shortenIIF() local
81 assert(GPRs != 0 && "Register must be a GPR"); in shortenIIF()
82 if (GPRs & LiveOther) in shortenIIF()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | asm-17.ll | 5 ; Test i32 GPRs.
16 ; Test i64 GPRs.
62 ; Test clobbers of GPRs and CC.
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| D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
57 ; Test 64-bit moves from GPRs to FPRs.
65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
90 ; Test 64-bit moves from FPRs to GPRs.
98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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| D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs.
5 ; This function should require all GPRs, but no other spill slots. The caller
81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | int-move-01.ll | 1 ; Test moves between GPRs.
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| D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | fp-move-09.ll | 1 ; Test moves between FPRs and GPRs for z196 and above.
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| D | frame-18.ll | 1 ; Test spilling of GPRs. The tests here assume z10 register pressure,
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| D | frame-09.ll | 41 ; This function should require all GPRs but no other spill slots.
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| D | frame-08.ll | 1 ; Test the saving and restoring of GPRs in large frames.
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| /external/libcxxabi/src/Unwind/ |
| D | Registers.hpp | 67 struct GPRs { struct in libunwind::Registers_x86
86 GPRs _registers;
92 _registers = *((GPRs *)registers); in Registers_x86()
255 struct GPRs { struct in libunwind::Registers_x86_64
278 GPRs _registers;
284 _registers = *((GPRs *)registers); in Registers_x86_64()
1047 struct GPRs { struct in libunwind::Registers_arm64
1056 GPRs _registers;
1332 struct GPRs { struct in libunwind::Registers_arm
1352 GPRs _registers;
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| /external/llvm/test/CodeGen/X86/ |
| D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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| D | mmx-arg-passing.ll | 8 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-align-long-double.ll | 4 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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| /external/llvm/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2013-04-16-AAPCS-C5-vs-VFP.ll | 4 ; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass
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| D | 2013-04-16-AAPCS-C4-vs-VFP.ll | 4 ; Our purpose: make NSAA != SP, and only after start to use GPRs.
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| D | domain-conv-vmovs.ll | 90 ; Check that the movement to and from GPRs takes place in the NEON domain.
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| D | vdup.ll | 287 ; the value isn't moved out to GPRs first.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 206 // GPRs without the PC. Some ARM instructions do not allow the PC in
216 // GPRs without the PC but with APSR. Some instructions allow accessing the
335 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
336 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
341 // Register class representing a pair of even-odd GPRs.
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| D | ARMCallingConv.td | 30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
117 // i64/f64 is passed in even pairs of GPRs
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 138 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
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| D | README.txt | 615 LR would be in a separate register class from the GPRs. The class of LR would be
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 300 // The first 4 MMX vector arguments are passed in GPRs.
623 // All GPRs - except r11
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| D | X86RegisterInfo.td | 335 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
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