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Searched refs:HRcVec128 (Results 1 – 13 of 13) sorted by relevance

/external/valgrind/main/VEX/priv/
Dhost_generic_regs.h106 HRcVec128=8 /* 128-bit SIMD */ enumerator
131 vassert(rc >= HRcInt32 && rc <= HRcVec128); in hregClass()
Dhost_generic_regs.c51 case HRcVec128: vex_printf("HRcVec128"); break; in ppHRegClass()
67 case HRcVec128: vex_printf("%%%sV%d", maybe_v, regNo); return; in ppHReg()
Dhost_ppc_defs.c81 case HRcVec128: in ppHRegPPC()
163 HReg hregPPC_VR0 ( void ) { return mkHReg( 0, HRcVec128, False); } in hregPPC_VR0()
164 HReg hregPPC_VR1 ( void ) { return mkHReg( 1, HRcVec128, False); } in hregPPC_VR1()
165 HReg hregPPC_VR2 ( void ) { return mkHReg( 2, HRcVec128, False); } in hregPPC_VR2()
166 HReg hregPPC_VR3 ( void ) { return mkHReg( 3, HRcVec128, False); } in hregPPC_VR3()
167 HReg hregPPC_VR4 ( void ) { return mkHReg( 4, HRcVec128, False); } in hregPPC_VR4()
168 HReg hregPPC_VR5 ( void ) { return mkHReg( 5, HRcVec128, False); } in hregPPC_VR5()
169 HReg hregPPC_VR6 ( void ) { return mkHReg( 6, HRcVec128, False); } in hregPPC_VR6()
170 HReg hregPPC_VR7 ( void ) { return mkHReg( 7, HRcVec128, False); } in hregPPC_VR7()
171 HReg hregPPC_VR8 ( void ) { return mkHReg( 8, HRcVec128, False); } in hregPPC_VR8()
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Dhost_arm_defs.c77 case HRcVec128: in ppHRegARM()
113 HReg hregARM_Q8 ( void ) { return mkHReg(8, HRcVec128, False); } in hregARM_Q8()
114 HReg hregARM_Q9 ( void ) { return mkHReg(9, HRcVec128, False); } in hregARM_Q9()
115 HReg hregARM_Q10 ( void ) { return mkHReg(10, HRcVec128, False); } in hregARM_Q10()
116 HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); } in hregARM_Q11()
117 HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); } in hregARM_Q12()
118 HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); } in hregARM_Q13()
119 HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); } in hregARM_Q14()
120 HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); } in hregARM_Q15()
2612 case HRcVec128: { in genSpill_ARM()
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Dhost_amd64_defs.c70 case HRcVec128: in ppHRegAMD64()
121 HReg hregAMD64_XMM0 ( void ) { return mkHReg( 0, HRcVec128, False); } in hregAMD64_XMM0()
122 HReg hregAMD64_XMM1 ( void ) { return mkHReg( 1, HRcVec128, False); } in hregAMD64_XMM1()
123 HReg hregAMD64_XMM3 ( void ) { return mkHReg( 3, HRcVec128, False); } in hregAMD64_XMM3()
124 HReg hregAMD64_XMM4 ( void ) { return mkHReg( 4, HRcVec128, False); } in hregAMD64_XMM4()
125 HReg hregAMD64_XMM5 ( void ) { return mkHReg( 5, HRcVec128, False); } in hregAMD64_XMM5()
126 HReg hregAMD64_XMM6 ( void ) { return mkHReg( 6, HRcVec128, False); } in hregAMD64_XMM6()
127 HReg hregAMD64_XMM7 ( void ) { return mkHReg( 7, HRcVec128, False); } in hregAMD64_XMM7()
128 HReg hregAMD64_XMM8 ( void ) { return mkHReg( 8, HRcVec128, False); } in hregAMD64_XMM8()
129 HReg hregAMD64_XMM9 ( void ) { return mkHReg( 9, HRcVec128, False); } in hregAMD64_XMM9()
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Dhost_x86_defs.c69 case HRcVec128: in ppHRegX86()
95 HReg hregX86_XMM0 ( void ) { return mkHReg(0, HRcVec128, False); } in hregX86_XMM0()
96 HReg hregX86_XMM1 ( void ) { return mkHReg(1, HRcVec128, False); } in hregX86_XMM1()
97 HReg hregX86_XMM2 ( void ) { return mkHReg(2, HRcVec128, False); } in hregX86_XMM2()
98 HReg hregX86_XMM3 ( void ) { return mkHReg(3, HRcVec128, False); } in hregX86_XMM3()
99 HReg hregX86_XMM4 ( void ) { return mkHReg(4, HRcVec128, False); } in hregX86_XMM4()
100 HReg hregX86_XMM5 ( void ) { return mkHReg(5, HRcVec128, False); } in hregX86_XMM5()
101 HReg hregX86_XMM6 ( void ) { return mkHReg(6, HRcVec128, False); } in hregX86_XMM6()
102 HReg hregX86_XMM7 ( void ) { return mkHReg(7, HRcVec128, False); } in hregX86_XMM7()
830 vassert(hregClass(dst) == HRcVec128); in X86Instr_SseConst()
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Dhost_amd64_isel.c203 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); in newVRegV()
322 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
323 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
2560 vassert(hregClass(r) == HRcVec128); in iselFltExpr()
2747 vassert(hregClass(r) == HRcVec128); in iselDblExpr()
3114 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
3726 vassert(hregClass(*rHi) == HRcVec128); in iselDVecExpr()
3727 vassert(hregClass(*rLo) == HRcVec128); in iselDVecExpr()
4918 hreg = mkHReg(j++, HRcVec128, True); in iselSB_AMD64()
4921 hreg = mkHReg(j++, HRcVec128, True); in iselSB_AMD64()
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Dhost_arm64_defs.c69 case HRcVec128: in ppHRegARM64()
122 HReg hregARM64_Q16 ( void ) { return mkHReg(16, HRcVec128, False); } in hregARM64_Q16()
123 HReg hregARM64_Q17 ( void ) { return mkHReg(17, HRcVec128, False); } in hregARM64_Q17()
124 HReg hregARM64_Q18 ( void ) { return mkHReg(18, HRcVec128, False); } in hregARM64_Q18()
1836 vassert(hregClass(src) == HRcVec128); in ARM64Instr_VMov()
1837 vassert(hregClass(dst) == HRcVec128); in ARM64Instr_VMov()
3250 case HRcVec128: { in genSpill_ARM64()
3291 case HRcVec128: { in genReload_ARM64()
3334 vassert(hregClass(r) == HRcVec128); in qregNo()
Dhost_generic_reg_alloc2.c211 case HRcVec128: case HRcFlt64: in sanity_check_spill_offset()
839 case HRcVec128: case HRcFlt64: in doRegisterAllocation()
Dhost_x86_isel.c234 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); in newVRegV()
301 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
302 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
3248 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
4478 case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); break; in iselSB_X86()
Dhost_arm64_isel.c171 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); in newVRegV()
4329 vassert(hregClass(r) == HRcVec128); in iselV128Expr()
7039 hreg = mkHReg(j++, HRcVec128, True); in iselSB_ARM64()
Dhost_ppc_isel.c359 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); in newVRegV()
1311 vassert(hregClass(vSrc) == HRcVec128); in isNan()
4705 vassert(hregClass(r) == HRcVec128); in iselVecExpr()
5994 case Ity_V128: hregLo = mkHReg(j++, HRcVec128, True); break; in iselSB_PPC()
Dhost_arm_isel.c185 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/); in newVRegV()
3779 vassert(hregClass(r) == HRcVec128); in iselNeonExpr()
6381 case Ity_V128: hreg = mkHReg(j++, HRcVec128, True); break; in iselSB_ARM()