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Searched refs:INSERT_SUBREG (Results 1 – 25 of 40) sorted by relevance

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/external/llvm/include/llvm/Target/
DTargetOpcodes.h49 INSERT_SUBREG = 7, enumerator
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1148 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1154 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1307 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1311 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1315 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1319 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1323 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1327 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1334 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2497 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
DAArch64AdvSIMDScalarPass.cpp243 else if (Use->getOpcode() == AArch64::INSERT_SUBREG || in isProfitableToTransform()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDGPUInstructions.td146 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
152 (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x)
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUInstructions.td146 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
152 (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x)
/external/llvm/test/CodeGen/X86/
Dcrash-nosse.ll5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
/external/llvm/lib/Target/R600/
DSIInstructions.td1773 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1814 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1844 (INSERT_SUBREG
1845 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2284 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2695 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2702 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2709 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2716 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub0),
2722 (INSERT_SUBREG
[all …]
DAMDGPUInstructions.td395 (INSERT_SUBREG $vec, $elem, sub_reg)
438 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
DSIFixSGPRCopies.cpp261 case AMDGPU::INSERT_SUBREG: { in runOnMachineFunction()
DSIInstrInfo.cpp684 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG; in getVALUOp()
751 case AMDGPU::INSERT_SUBREG: in canReadVGPR()
987 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) { in legalizeOperands()
1324 case AMDGPU::INSERT_SUBREG: in moveToVALU()
DR600OptimizeVectorRegisters.cpp195 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG), in RebuildVector()
DR600Instructions.td478 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
484 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td80 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
347 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
354 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32),
360 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
367 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp218 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp266 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
306 case TargetOpcode::INSERT_SUBREG: in reserveResources()
DScheduleDAGRRList.cpp1893 Opc == TargetOpcode::INSERT_SUBREG) in getNodePriority()
2112 Opc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2141 POpc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2585 Opc == TargetOpcode::INSERT_SUBREG) in canEnableCoalescing()
2956 SuccOpc == TargetOpcode::INSERT_SUBREG || in AddPseudoTwoAddrDeps()
DInstrEmitter.cpp521 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
714 Opc == TargetOpcode::INSERT_SUBREG || in EmitMachineNode()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h712 return getOpcode() == TargetOpcode::INSERT_SUBREG;
755 case TargetOpcode::INSERT_SUBREG:
/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp54 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
106 case TargetOpcode::INSERT_SUBREG: in reserveResources()
/external/llvm/test/CodeGen/Thumb2/
Dcrash.ll28 ; The first INSERT_SUBREG needs an <undef> use operand for that to work.
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td931 (INSERT_SUBREG
935 (INSERT_SUBREG
940 (INSERT_SUBREG
944 (INSERT_SUBREG
949 (INSERT_SUBREG
953 (INSERT_SUBREG
DX86InstrAVX512.td328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
[all …]
/external/llvm/test/CodeGen/R600/
Dinsert_vector_elt.ll177 ; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp504 TII->get(TargetOpcode::INSERT_SUBREG), Out) in createInsertSubreg()
DARMInstrNEON.td4171 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4175 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
5505 (v16i8 (INSERT_SUBREG QPR:$src1,
5511 (v8i16 (INSERT_SUBREG QPR:$src1,
5517 (v4i32 (INSERT_SUBREG QPR:$src1,
5524 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5527 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5531 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5533 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5536 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
[all …]

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