Home
last modified time | relevance | path

Searched refs:IR (Results 1 – 25 of 573) sorted by relevance

12345678910>>...23

/external/clang/test/PCH/
Dobjc_container.m8 // RUN: %clang_cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
17 // CHECK-IR: define void @all() #0
18 // CHECK-IR: {{call.*objc_msgSend}}
19 // CHECK-IR: {{call.*objc_msgSend}}
20 // CHECK-IR: {{call.*objc_msgSend}}
21 // CHECK-IR: {{call.*objc_msgSend}}
22 // CHECK-IR: ret void
24 // CHECK-IR: attributes #0 = { nounwind {{.*}} }
25 // CHECK-IR: attributes #1 = { nonlazybind }
Dobjc_literals.m4 // RUN: %clang_cc1 -include-pch %t -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
42 // CHECK-IR: define internal void @test_numeric_literals()
45 // CHECK-IR: {{call.*17}}
48 // CHECK-IR: {{call.*1.745}}
Dobjc_literals.mm4 …include-pch %t -x objective-c++ -std=c++0x -emit-llvm -o - %s | FileCheck -check-prefix=CHECK-IR %s
53 // CHECK-IR: define linkonce_odr void @_Z29variadic_dictionary_expansionIJP8NSStringS1_EJP8NSNumber…
57 // CHECK-IR: {{call.*objc_msgSend}}
58 // CHECK-IR: ret void
/external/llvm/lib/IR/
DMakefile13 BUILT_SOURCES = $(PROJ_OBJ_ROOT)/include/llvm/IR/Intrinsics.gen
17 GENFILE:=$(PROJ_OBJ_ROOT)/include/llvm/IR/Intrinsics.gen
19 INTRINSICTD := $(PROJ_SRC_ROOT)/include/llvm/IR/Intrinsics.td
20 INTRINSICTDS := $(wildcard $(PROJ_SRC_ROOT)/include/llvm/IR/Intrinsics*.td)
26 $(GENFILE): $(ObjDir)/Intrinsics.gen.tmp $(PROJ_OBJ_ROOT)/include/llvm/IR/.dir
32 $(Echo) Installing $(DESTDIR)$(PROJ_includedir)/llvm/IR/Intrinsics.gen
33 $(Verb) $(DataInstall) $(GENFILE) $(DESTDIR)$(PROJ_includedir)/llvm/IR/Intrinsics.gen
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
Dsplit-gep-and-gvn.ll2 ; RUN: opt < %s -S -separate-const-offset-from-gep -gvn -dce | FileCheck %s --check-prefix=IR
53 ; IR-LABEL: @sum_of_array(
54 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array,…
55 ; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
56 ; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
57 ; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 33
96 ; IR-LABEL: @sum_of_array2(
97 ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr inbounds [32 x [32 x float]] addrspace(3)* @array,…
98 ; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 1
99 ; IR: getelementptr float addrspace(3)* [[BASE_PTR]], i64 32
[all …]
/external/chromium_org/third_party/mesa/src/src/glsl/
DREADME17 ir.h for the IR structures.
35 7) The driver performs code generation out of the IR, taking a linked
37 ir_to_mesa.cpp for Mesa IR code generation.
41 Q: What is HIR versus IR versus LIR?
44 high-level IR ("HIR"), with things like matrix operations, structure
49 producing a low level IR ("LIR").
54 accesses, and matrix multiplication broken down. The Mesa IR backend
57 shader IR backend could potentially even handle some matrix operations
58 without breaking them down, but the 965 fragment shader IR backend
61 low-level IR that will make everyone happy. So that usage has fallen
[all …]
/external/mesa3d/src/glsl/
DREADME17 ir.h for the IR structures.
35 7) The driver performs code generation out of the IR, taking a linked
37 ir_to_mesa.cpp for Mesa IR code generation.
41 Q: What is HIR versus IR versus LIR?
44 high-level IR ("HIR"), with things like matrix operations, structure
49 producing a low level IR ("LIR").
54 accesses, and matrix multiplication broken down. The Mesa IR backend
57 shader IR backend could potentially even handle some matrix operations
58 without breaking them down, but the 965 fragment shader IR backend
61 low-level IR that will make everyone happy. So that usage has fallen
[all …]
/external/valgrind/main/docs/internals/
D3_2_BUGSTATUS.txt62 137714 vx1787 x86/amd64->IR: 0x66 0xF 0xF7 0xC6 (maskmovq, maskmovdq)
81 147498 vx1795 amd64->IR: 0xF0 0xF 0xB0 0xF (lock cmpxchg %cl,(%rdi))
89 148363 marginal amd64->IR: 0x65 0x4C 0x8B 0x1C (mov %gs:0x10,%r11)
95 149838 marginal x86->IR: 0xF 0xAE 0xD 0xE0 (FXRSTOR ?)
119 152501 vx1800 vex x86->IR: 0x27 0x66 0x89 0x45 (daa)
120 152818 vx1801 vex x86->IR: 0xF3 0xAC 0xFC 0x9C (rep lodsb)
176 vx1737 vx1752 32 n-i-bz x86->IR: 26 2E 64 65 90 %es:%cs:%fs:%gs:nop
289 pending pending s93 133962 amd64->IR: 0xF2 0x4C 0xF 0x10 (rex64X ...)
291 pending pending s93 135023 amd64->IR: 0x49 0xDD 0x86 0xE0
317 pending pending 135264 ppc->IR: dcbzl instruction missing
[all …]
D3_1_BUGSTATUS.txt30 vx1604 fixed 124499 amd64->IR: 0xF 0xE 0x48 0x85 (femms)
32 wontfix 124697 vex x86->IR: 0xF 0x70 0xC9 0x0 (pshufw)
33 vx1603 fixed 124892 vex x86->IR: 0xF3 0xAE (REPx SCASB)
37 vx1602 fixed n-i-bz amd64->IR: 0x66 0xF 0xF5 (pmaddwd)
43 vx1612 fixed 125607 amd64->IR: 0x66 0xF 0xA3 0x2 (btw etc)
44 vx1613 fixed 125651 amd64->IR: 0xF8 0x49 0xFF 0xE3 (clc?)
56 vx1611 fixed 126243 vex x86->IR: popw mem
57 low 125265 vex x86->IR: 0xD9 0xD0 (fnop)
58 low 126257 vex x86->IR: 0xF2 0x0F 0xF0 0x40 (lddqu) (sse3)
59 low 126258 vex x86->IR: 0xDF 0x4D (fisttp) (sse3)
[all …]
D3_0_BUGSTATUS.txt112 113015 vex amd64->IR: 0xE3 0x14 0x48 0x83 (jrcxz)
153 113851 vex x86->IR: (pmaddwd): 0x66 0xF 0xF5 0xC7
163 114412 vex amd64->IR: 0xF 0xAD 0xC2 0xD3 (128-bit shift, shrdq?)
168 114455 vex amd64->IR: 0xF 0xAC 0xD0 0x1 (also shrdq)
173 115590: amd64->IR: 0x67 0xE3 0x9 0xEB (address size override)
228 111724 vex amd64->IR: unhandled instruction bytes: 0x41 0xF 0xAB
243 111748 vex amd64->IR: unhandled instruction bytes: fucom
256 111829 vex x86->IR: unhandled instruction bytes: sbb Al, Ib
262 111851 vex x86->IR: unhandled instruction bytes: 0x9F 0x89
289 112501 vex x86->IR: movq (0xF 0x7F 0xC1 0xF) (mmx MOVQ)
[all …]
D3_7_BUGSTATUS.txt87 291924 vex x86->IR: unhandled instruction bytes: 0x66 0xF 0x38 0x31
94 293855 vex amd64->IR: 0x2F 0x55 0x73 0x65 0x72 0x73 0x2F 0x6A
117 251569 rdtscp not supported: vex amd64->IR: 0xF 0x1 0xF9 0x8B 0x4C 0x24
131 295808 vex amd64->IR: 0xF3 0xF 0xBC 0xC0 0x48 0x1 0xD0 0x48 (TZCNT)
151 296577 vex x86->IR: 0x66 0xF 0x3A 0x17
154 296578 vex amd64->IR: 0x60 0x0 0x0 0x0 0x0 0x0 0x0 0x0
157 296947 vex amd64->IR: 0x1F 0x7 0x0 0x0 0x0 0x0
176 301011 vex x86->IR: 0xF3 0xF 0xBC 0xDE (TZCNT)
191 301967 vex x86->IR: 0xC5 0xF9 0x6E 0x40 (AVX in 32-bit mode)
D3_3_BUGSTATUS.txt41 126255 Wont pend vex x86->IR: 0xDF 0x75 (fbstp) (x87 BCD stores)
126 167700 HIGH,WF pend vex x86->IR: unhandled instruction bytes: 0xD5 0x36 0x5B
225 172417 Fixd vx1867 x86->IR: 0x82 ...
227 172563 Fixd vx???? amd64->IR: 0xD9 0xF5 - fprem1
234 173751 Fixd vx1876 amd64->IR: 0x48 0xF 0x6F 0x45
237 174532 WF DUP amd64->IR: 0x48 0xF 0xED 0x0
244 175150 Fixd vx1873 x86->IR: 0xF2 0xF 0x11 0xC1 (movss xmm1, xmm0)
281 vx1836/7 vx1845 Vfd 126389 vex x86->IR: 0xF 0xAE (FXRSTOR)
284 vx1838 vx1846 Vfd 152818 vex x86->IR: 0xF3 0xAC (repz lodsb)
286 vx1834 vx1843 Vfd 153196 vex x86->IR: 0xF2 0xA6 (repnz cmpsb)
[all …]
/external/llvm/include/llvm/
Dmodule.modulemap70 umbrella "IR"
73 // We cannot have llvm/PassManager.h and llvm/IR/PassManager.h in the same TU,
74 // so we can't include llvm/IR/PassManager.h in the IR module.
75 exclude header "IR/PassManager.h"
76 exclude header "IR/LegacyPassManager.h"
79 exclude header "IR/Instruction.def"
85 module Implementation { header "IR/LegacyPassManager.h" export * }
91 header "IR/PassManager.h"
/external/llvm/include/llvm/IR/
DPassManager.h173 virtual PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) = 0;
228 PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) override {
229 return Pass.run(IR, AM);
254 PreservedAnalyses run(IRUnitT IR, AnalysisManagerT *AM) override {
255 return Pass.run(IR);
278 virtual bool invalidate(IRUnitT IR, const PreservedAnalyses &PA) = 0;
363 bool invalidate(IRUnitT IR, const PreservedAnalyses &PA) override {
364 return Result.invalidate(IR, PA);
382 run(IRUnitT IR, AnalysisManagerT *AM) = 0;
422 run(IRUnitT IR, AnalysisManagerT *AM) override {
[all …]
/external/iptables/extensions/
Dlibip6t_icmp6.man7 .IR type ,
8 .IR type
10 .IR code ,
/external/bzip2/
Dbzgrep.110 .IR filename ".\|.\|."
15 .IR filename ".\|.\|."
20 .IR filename ".\|.\|."
22 .IR Bzgrep
Dbzdiff.126 .IR diff "."
30 .IR file1 ".bz2."
34 .IR diff "."
/external/bison/doc/
Dbison.x7 .IR yacc (1).
10 .IR yacc .
17 .IR yacc ,
30 .IR yacc 's
/external/chromium_org/third_party/icu/source/data/mappings/
Dnoop-iso-ir-165.ucm8 # Name: "Fake" Unicode to ISO-IR-165 table
11 # This is not a real ISO-IR-165 table, but a "fake" table to return U+FFFD
12 # for every byte sequence valid in ISO-IR-165. Chrome and Android
/external/icu/icu4c/source/data/mappings/
Dnoop-iso-ir-165.ucm8 # Name: "Fake" Unicode to ISO-IR-165 table
11 # This is not a real ISO-IR-165 table, but a "fake" table to return U+FFFD
12 # for every byte sequence valid in ISO-IR-165. Chrome and Android
/external/chromium_org/third_party/closure_compiler/runner/src/com/google/javascript/jscomp/
DChromePass.java8 import com.google.javascript.rhino.IR;
135 Node definitionNode = IR.exprResult(getPropNode).srcref(parent); in visitPropertyDefinition()
145 return IR.string("string"); in getTypeByCrPropertyKind()
148 return IR.string("boolean"); in getTypeByCrPropertyKind()
241 IR.exprResult(methodDeclaration).srcrefTree(exprResult), in maybeAddPublicDeclaration()
395 Node exprResult = IR.exprResult( in visit()
396 IR.assign(buildQualifiedName(n.getFirstChild()), functionTree).srcref(n) in visit()
420 exprResult = IR.exprResult(buildQualifiedName(n)).srcref(parent); in visit()
422 exprResult = IR.exprResult( in visit()
423 IR.assign(buildQualifiedName(n), varContent).srcref(parent) in visit()
/external/clang/lib/Rewrite/Core/
DDeltaTree.cpp132 DeltaTreeInteriorNode(const InsertResult &IR) in DeltaTreeInteriorNode() argument
134 Children[0] = IR.LHS; in DeltaTreeInteriorNode()
135 Children[1] = IR.RHS; in DeltaTreeInteriorNode()
136 Values[0] = IR.Split; in DeltaTreeInteriorNode()
137 FullDelta = IR.LHS->getFullDelta()+IR.RHS->getFullDelta()+IR.Split.Delta; in DeltaTreeInteriorNode()
/external/llvm/test/CodeGen/AArch64/
Dneon-truncStore-extLoad.ll4 ; Test a trunc IR and a vector store IR can be selected correctly.
33 ; Test a vector load IR and a sext/zext IR can be selected correctly.
/external/llvm/test/CodeGen/NVPTX/
Daccess-non-generic.ll3 ; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR
17 ; IR-LABEL: @ld_st_shared_f32
18 ; IR-NOT: addrspacecast
80 ; IR-LABEL: @ld_int_from_float
81 ; IR: load i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*)
/external/llvm/
Dllvm-gen-intrinsics.mk2 INTRINSICTD := $(LLVM_ROOT_PATH)/include/llvm/IR/Intrinsics.td
11 GENFILE := $(addprefix $(call local-generated-sources-dir)/llvm/IR/,Intrinsics.gen)

12345678910>>...23