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Searched refs:MRM0m (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h300 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 enumerator
686 case X86II::MRM0m: case X86II::MRM1m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp823 case X86II::MRM0m: case X86II::MRM1m: in EmitVEXOpcodePrefix()
1067 case X86II::MRM0m: case X86II::MRM1m: in DetermineREXPrefix()
1442 case X86II::MRM0m: case X86II::MRM1m: in EncodeInstruction()
1452 EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m, in EncodeInstruction()
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td523 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
527 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
531 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
535 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
540 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
544 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
548 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
552 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
558 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
562 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrFPStack.td217 defm ADD : FPBinary<fadd, MRM0m, "add">;
443 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src",
445 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src",
449 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src",
451 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src",
639 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
641 def FXSAVE64 : RI<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
DX86InstrSystem.td393 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
395 def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
397 def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
407 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
416 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
DX86InstrArithmetic.td520 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
523 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
527 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
531 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
538 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
542 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1230 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1275 def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
1276 def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
1277 def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
[all …]
DX86Instr3DNow.td90 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
DX86CodeEmitter.cpp217 case X86II::MRM0m: case X86II::MRM1m: in determineREX()
902 case X86II::MRM0m: case X86II::MRM1m: in emitVEXOpcodePrefix()
1342 case X86II::MRM0m: case X86II::MRM1m: in emitInstruction()
1354 emitMemModRMByte(MI, CurOp, (Form==X86II::MRMXm) ? 0 : Form - X86II::MRM0m, in emitInstruction()
DX86InstrInfo.td949 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
953 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1003 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1216 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1219 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1222 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1225 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
DX86InstrCompiler.td629 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
656 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
DX86InstrFormats.td33 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
DX86InstrSSE.td3775 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp97 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, enumerator
707 case X86Local::MRM0m: in emitInstructionSpecifier()
829 case X86Local::MRM0m: case X86Local::MRM1m: in emitDecodePath()
833 filter = new ExtendedFilter(false, Form - X86Local::MRM0m); in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td55 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1826 case X86II::MRM0m: case X86II::MRM1m: // for instructions that operate on