Searched refs:MTHC1 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | ret.ll | 10 … %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-…
11 …t < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-…
12 …inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
151 ; NO-MTHC1-DAG: mtc1 $zero, $f0
153 ; MTHC1-DAG: mtc1 $zero, $f0
180 ; NO-MTHC1-DAG: mtc1 $zero, $f0
181 ; NO-MTHC1-DAG: mtc1 $zero, $f1
183 ; MTHC1-DAG: mtc1 $zero, $f0
184 ; MTHC1-DAG: mthc1 $zero, $f0
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| /external/chromium_org/v8/src/mips/ |
| D | constants-mips.h | 451 MTHC1 = ((0 << 3) + 7) << 21, enumerator
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| D | disasm-mips.cc | 475 case MTHC1: in DecodeTypeRegister()
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| D | simulator-mips.cc | 1903 case MTHC1: in ConfigureTypeRegister()
2200 case MTHC1: in DecodeTypeRegister()
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| D | assembler-mips.cc | 2016 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
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| /external/chromium_org/v8/src/mips64/ |
| D | constants-mips64.h | 464 MTHC1 = ((0 << 3) + 7) << 21, enumerator
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| D | disasm-mips64.cc | 503 case MTHC1: in DecodeTypeRegister()
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| D | simulator-mips64.cc | 1974 case MTHC1: in ConfigureTypeRegister()
2338 case MTHC1: in DecodeTypeRegister()
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| D | assembler-mips64.cc | 2232 GenInstrRegister(COP1, MTHC1, rt, fs, f0); in mthc1()
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