| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 179 case ISD::MULHU: in Select()
184 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; in Select()
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| D | SparcISelLowering.cpp | 1551 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 199 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
211 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
224 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
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| D | AMDILISelLowering.cpp | 174 setOperationAction(ISD::MULHU, MVT::i64, Expand); in InitAMDILLowering()
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 199 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
211 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
224 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
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| D | AMDILISelLowering.cpp | 174 setOperationAction(ISD::MULHU, MVT::i64, Expand); in InitAMDILLowering()
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 307 case ISD::MULHU: { in selectNode()
308 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in selectNode()
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| D | MipsSEISelLowering.cpp | 119 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
162 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
207 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
364 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 297 MULHU, MULHS, enumerator
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| D | SelectionDAG.h | 1024 case ISD::MULHU:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2738 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2739 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
2740 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT)); in BuildUDIV()
2793 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL()
2829 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
2878 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
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| D | SelectionDAGDumper.cpp | 164 case ISD::MULHU: return "mulhu"; in getOperationName()
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| D | LegalizeDAG.cpp | 3663 case ISD::MULHU: in ExpandNode()
3665 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : in ExpandNode()
3692 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); in ExpandNode()
3794 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode()
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| D | LegalizeVectorTypes.cpp | 1574 case ISD::MULHU: in WidenVectorResult()
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| D | DAGCombiner.cpp | 1209 case ISD::MULHU: return visitMULHU(N); in visit()
2376 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); in visitUMUL_LOHI()
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| D | SelectionDAG.cpp | 3122 case ISD::MULHU: in getNode()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 276 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
1540 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1552 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1565 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 142 setOperationAction(ISD::MULHU, MVT::i8, Expand); in MSP430TargetLowering()
147 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 321 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 106 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 175 setOperationAction(ISD::MULHU, VT, Expand); in SystemZTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand); in AArch64TargetLowering()
1176 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 436 setOperationAction(ISD::MULHU, VT, Expand); in resetOperationActions()
843 setOperationAction(ISD::MULHU, VT, Expand); in resetOperationActions()
958 setOperationAction(ISD::MULHU, MVT::v8i16, Legal); in resetOperationActions()
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal); in resetOperationActions()
13597 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 415 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand); in ARMTargetLowering()
613 setOperationAction(ISD::MULHU, MVT::i32, Expand); in ARMTargetLowering()
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