| /external/apache-xml/src/main/java/org/apache/xpath/compiler/ |
| D | OpCodes.java | 258 public static final int OP_NEG = 16; field in OpCodes
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| D | Compiler.java | 153 case OpCodes.OP_NEG : in compile()
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| D | XPathParser.java | 1137 appendOp(2, OpCodes.OP_NEG); in UnaryExpr()
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| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 224 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
475 case OP_NEG: in isModSupported()
627 case OP_NEG: in getThroughput()
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| D | nv50_ir_emit_nvc0.cpp | 810 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg(); in emitCVT()
1660 case OP_NEG: in emitInstruction()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| D | nv50_ir_target_nvc0.cpp | 224 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
475 case OP_NEG: in isModSupported()
627 case OP_NEG: in getThroughput()
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| D | nv50_ir_emit_nvc0.cpp | 810 const bool neg = (i->op == OP_NEG) || i->src(0).mod.neg(); in emitCVT()
1660 case OP_NEG: in emitInstruction()
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_peephole.cpp | 299 case OP_NEG: in findOriginForTestWithZero()
378 case NV50_IR_MOD_NEG: return OP_NEG; in getOp()
528 case OP_NEG: res.data.f32 = -imm.reg.data.f32; break; in unary()
720 i->op = OP_NEG; in opnd()
747 bld.mkOp1(OP_NEG, TYPE_S32, i->getDef(0), tB); in opnd()
808 case OP_NEG: in opnd()
862 mi->op != OP_NEG)) in visit()
876 if ((i->op == OP_NEG) && mod.neg()) { in visit()
957 if (neg && neg->op != OP_NEG) { in handleABS()
961 if (!neg || neg->op != OP_NEG || in handleABS()
[all …]
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| D | nv50_ir_target_nv50.cpp | 92 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
410 case OP_NEG: in isModSupported()
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| D | nv50_ir_emit_nv50.cpp | 1211 case OP_NEG: code[1] |= 1 << 29; break; in emitCVT()
1609 case OP_NEG: in emitInstruction()
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| D | nv50_ir.h | 60 OP_NEG, enumerator
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| D | nv50_ir.cpp | 37 case OP_NEG: bits = NV50_IR_MOD_NEG; break; in Modifier()
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| D | nv50_ir_from_sm4.cpp | 395 case SM4_OPCODE_INEG: return OP_NEG; in cvtOpcode()
1364 res = mkOp1v(OP_NEG, sTy, getSSA(res->reg.size), res); in src()
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| D | nv50_ir_lowering_nv50.cpp | 449 bld.mkOp1(OP_NEG, ty, s, q)->setPredicate(CC_S, cond); in handleDIV()
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| D | nv50_ir_from_tgsi.cpp | 1236 val = mkOp1v(OP_NEG, ty, getScratch(), val); in applySrcMod()
1937 mkOp1(OP_NEG, TYPE_F32, val0, val0); in handleInstruction()
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_peephole.cpp | 299 case OP_NEG: in findOriginForTestWithZero()
378 case NV50_IR_MOD_NEG: return OP_NEG; in getOp()
528 case OP_NEG: res.data.f32 = -imm.reg.data.f32; break; in unary()
720 i->op = OP_NEG; in opnd()
747 bld.mkOp1(OP_NEG, TYPE_S32, i->getDef(0), tB); in opnd()
808 case OP_NEG: in opnd()
862 mi->op != OP_NEG)) in visit()
876 if ((i->op == OP_NEG) && mod.neg()) { in visit()
957 if (neg && neg->op != OP_NEG) { in handleABS()
961 if (!neg || neg->op != OP_NEG || in handleABS()
[all …]
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| D | nv50_ir_target_nv50.cpp | 92 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x1, 0x0 },
410 case OP_NEG: in isModSupported()
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| D | nv50_ir_emit_nv50.cpp | 1211 case OP_NEG: code[1] |= 1 << 29; break; in emitCVT()
1609 case OP_NEG: in emitInstruction()
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| D | nv50_ir.h | 60 OP_NEG, enumerator
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| D | nv50_ir.cpp | 37 case OP_NEG: bits = NV50_IR_MOD_NEG; break; in Modifier()
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| D | nv50_ir_from_sm4.cpp | 395 case SM4_OPCODE_INEG: return OP_NEG; in cvtOpcode()
1364 res = mkOp1v(OP_NEG, sTy, getSSA(res->reg.size), res); in src()
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| D | nv50_ir_lowering_nv50.cpp | 449 bld.mkOp1(OP_NEG, ty, s, q)->setPredicate(CC_S, cond); in handleDIV()
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| D | nv50_ir_from_tgsi.cpp | 1236 val = mkOp1v(OP_NEG, ty, getScratch(), val); in applySrcMod()
1937 mkOp1(OP_NEG, TYPE_F32, val0, val0); in handleInstruction()
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| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 394 def OP_NEG : Op<(op "-", $p0)>;
764 def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>;
904 def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>;
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