| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
190 assert(Offset2 > Offset1 in shouldScheduleLoadsNear()
195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 110 int64_t Offset1, int64_t Offset2,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 188 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
190 assert(Offset2 > Offset1 in shouldScheduleLoadsNear()
195 return (NumLoads < 16 && (Offset2 - Offset1) < 16); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 110 int64_t Offset1, int64_t Offset2,
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstrInfo.cpp | 219 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
221 assert(Offset2 > Offset1 in shouldScheduleLoadsNear()
226 return (NumLoads < 16 && (Offset2 - Offset1) < 16); in shouldScheduleLoadsNear()
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| D | AMDGPUInstrInfo.h | 124 int64_t Offset1, int64_t Offset2,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.cpp | 231 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
232 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
233 Offset1 == Offset2) in ClusterNeighboringLoads()
237 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
238 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
241 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| D | DAGCombiner.cpp | 7773 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); in CombineToPreIndexedLoadStore() local
7784 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; in CombineToPreIndexedLoadStore()
7785 else CNV = CNV - Offset1; in CombineToPreIndexedLoadStore()
11499 int64_t Offset1, Offset2; in isAlias() local
11503 Base1, Offset1, GV1, CV1); in isAlias()
11509 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
11510 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
11518 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); in isAlias()
11520 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 || in isAlias()
11521 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1); in isAlias()
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| D | SelectionDAG.cpp | 6508 int64_t Offset1 = 0; in isConsecutiveLoad() local
6511 bool isGA1 = TLI->isGAPlusOffset(Loc.getNode(), GV1, Offset1); in isConsecutiveLoad()
6514 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 345 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
357 int64_t Offset1, int64_t Offset2,
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| D | X86InstrInfo.cpp | 4831 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
4927 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); in areLoadsFromSameBasePtr()
4936 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
4938 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
4939 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 148 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
160 int64_t Offset1, int64_t Offset2,
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| D | ARMBaseInstrInfo.cpp | 1429 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1490 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1510 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1515 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
1517 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 635 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
648 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /external/llvm/test/CodeGen/SPARC/ |
| D | 64abi.ll | 433 ; CHECK-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]]
435 ; CHECK-DAG: ldx [%sp+[[Offset1]]], %o3
447 ; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
450 ; CHECK: ld [%fp+[[Offset1]]], %f1
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| /external/llvm/lib/Transforms/Scalar/ |
| D | MemCpyOptimizer.cpp | 117 int64_t Offset1 = GetOffsetFromIndex(GEP1, Idx, VariableIdxFound, TD); in IsPointerOffset() local
121 Offset = Offset2-Offset1; in IsPointerOffset()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 8069 int Offset1, int Offset2, int Offset4, int Offset8> {
8089 !cast<Operand>("GPR64pi" # Offset1)>;
8092 !cast<Operand>("GPR64pi" # Offset1)>;
8112 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8113 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 7300 int64_t Offset1 = 0; in isConsecutiveLS() local
7302 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); in isConsecutiveLS()
7305 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLS()
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