Searched refs:PRE_INC (Results 1 – 11 of 11) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 722 PRE_INC, enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 809 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
845 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
865 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
940 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1348 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1450 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in SelectARMIndexedLoad()
1524 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in SelectT2IndexedLoad()
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| D | ARMISelLowering.cpp | 593 for (unsigned im = (unsigned)ISD::PRE_INC; in ARMTargetLowering()
10138 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 332 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
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| D | DAGCombiner.cpp | 7596 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
7604 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
[all …]
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| D | PPCISelDAGToDAG.cpp | 1068 if (LD->getAddressingMode() != ISD::PRE_INC) in Select()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 774 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
784 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 728 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 320 for (unsigned im = (unsigned)ISD::PRE_INC; in AArch64TargetLowering()
541 for (unsigned im = (unsigned)ISD::PRE_INC; in addTypeForNEON()
7864 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
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| D | AArch64ISelDAGToDAG.cpp | 906 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in SelectIndexedLoad()
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