| /external/llvm/test/Analysis/BlockFrequencyInfo/ |
| D | double_exit.ll | 15 ; Pseudo-edges = exit
16 ; Pseudo-mass = 1
28 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
29 ; Pseudo-mass = 2/3
88 ; Pseudo-edges = exit
89 ; Pseudo-mass = 1
101 ; Pseudo-edges = outer.inc
102 ; Pseudo-mass = 1/2
114 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
115 ; Pseudo-mass = 2/3
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
90 def VAARG_64 : I<0, Pseudo,
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
[all …]
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| D | X86InstrTSX.td | 22 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
|
| /external/bison/m4/ |
| D | isnanl.m4 | 200 /* The isnanl function should recognize Pseudo-NaNs, Pseudo-Infinities,
201 Pseudo-Zeroes, Unnormalized Numbers, and Pseudo-Denormals, as defined in
207 { /* Pseudo-NaN. */
213 { /* Pseudo-Infinity. */
219 { /* Pseudo-Zero. */
231 { /* Pseudo-Denormal. */
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 86 // Pseudo valuetype mapped to the current pointer size to any address space.
90 // Pseudo valuetype to represent "vector of any size"
93 // Pseudo valuetype to represent "float of any format"
96 // Pseudo valuetype to represent "integer of any bit width"
99 // Pseudo valuetype mapped to the current pointer size.
|
| /external/llvm/test/MC/Mips/ |
| D | mips-noat.s | 15 …lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, wh…
29 …lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, wh…
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
194 def ATOMIC_LOAD_ADD_I64 : Pseudo<
197 def ATOMIC_LOAD_SUB_I64 : Pseudo<
200 def ATOMIC_LOAD_OR_I64 : Pseudo<
203 def ATOMIC_LOAD_XOR_I64 : Pseudo<
206 def ATOMIC_LOAD_AND_I64 : Pseudo<
209 def ATOMIC_LOAD_NAND_I64 : Pseudo<
213 def ATOMIC_CMP_SWAP_I64 : Pseudo<
217 def ATOMIC_SWAP_I64 : Pseudo<
236 def TCRETURNdi8 :Pseudo< (outs),
[all …]
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| D | PPCInstrInfo.td | 864 // Pseudo-instructions:
868 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
870 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
874 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
879 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
890 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
894 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
898 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
901 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
904 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
[all …]
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsBaseInfo.h | 105 Pseudo = 0, enumerator
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 317 // Pseudo-registers representing odd-even pairs of D registers. The even-odd
335 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
346 // Pseudo-registers representing 3 consecutive D registers.
357 // Pseudo 256-bit registers to represent pairs of Q registers. These should
362 // Pseudo 256-bit vector register class to model pairs of Q registers
381 // Pseudo 512-bit registers to represent four consecutive Q registers.
385 // Pseudo 512-bit vector register class to model 4 consecutive Q registers
394 // Pseudo-registers representing 2-spaced consecutive D registers.
|
| D | ARMScheduleSwift.td | 1197 // Pseudo instructions.
1915 (instregex "VLD2(d|q|b)(8|16|32)$", "VLD2q(8|16|32)Pseudo$")>;
1951 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
1958 "VLD2LN(d|q)(8|16|32)Pseudo$")>;
1972 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
1983 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
2015 (instregex "VST2q(8|16|32)$", "VST2q(8|16|32)Pseudo$")>;
2033 (instregex "VST1LNd(8|16|32)$", "VST1LNq(8|16|32)Pseudo$")>;
2038 (instregex "VST2LN(d|q)(8|16|32)$", "VST2LN(d|q)(8|16|32)Pseudo$")>;
2044 (instregex "VST3LN(d|q)(8|16|32)$", "VST3LN(d|q)(8|16|32)Pseudo$")>;
[all …]
|
| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 103 Pseudo, enumerator
223 return Flags & (1 << MCID::Pseudo); in isPseudo()
|
| /external/chromium_org/native_client_sdk/doc_generated/_static/ |
| D | pygments.css | 24 .highlight .kp { color: #007020 } /* Keyword.Pseudo */
58 .highlight .bp { color: #007020 } /* Name.Builtin.Pseudo */
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.h | 30 Pseudo = (1<<0), enumerator
|
| D | SparcInstrInfo.td | 302 // Pseudo instructions.
303 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
311 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
315 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
318 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
347 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
351 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
356 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
361 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
369 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
[all …]
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFormats.td | 1341 // Pseudo instructions
1350 class Pseudo<dag outs, dag ins, list<dag> pattern>
1359 : Pseudo<(outs cls:$R1), (ins imm:$I2),
1366 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
1379 : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
1388 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
1396 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
1415 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
1421 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
1432 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
[all …]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILInstrInfo.td | 185 "; i32 Pseudo branch instruction",
189 "; f32 Pseudo branch instruction",
222 "; Pseudo unconditional branch instruction",
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| D | AMDILInstrInfo.td | 185 "; i32 Pseudo branch instruction",
189 "; f32 Pseudo branch instruction",
222 "; Pseudo unconditional branch instruction",
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFormats.td | 31 def Pseudo : Format<0>;
102 // Mips Pseudo Instructions Format
105 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
110 // Mips32/64 Pseudo Instruction Format
117 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
[all …]
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| D | MSP430InstrFormats.td | 206 // Pseudo instructions
207 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86BaseInfo.h | 228 Pseudo = 0, enumerator
652 case X86II::Pseudo: in getMemoryOperandNo()
|
| /external/chromium_org/third_party/cython/src/Cython/Includes/libc/ |
| D | stdlib.pxd | 22 # 7.20.2 Pseudo-random sequence generation functions
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMBaseInfo.h | 340 Pseudo = 0 << FormShift, enumerator
|
| /external/chromium_org/third_party/mt19937ar/ |
| D | readme-mt.txt | 68 Pseudo-Random Number Generator",
|