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/external/valgrind/main/none/tests/mips32/
DLoadStore1.stdout.exp-LE2 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
3 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
4 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27
5 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027
6 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff
7 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff
8 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
9 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00
10 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
11 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
[all …]
DLoadStore.stdout.exp-BE2 sb $t0, 0($t1) :: RTval: 0x0, out: 0x0
3 sb $t0, 0($t1) :: RTval: 0x0, out: 0x1f1e1f
4 sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
5 sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f1e1f
6 sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff000000
7 sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff1f1e1f
8 sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
9 sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x1f1e1f
10 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
11 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1f0000
[all …]
DLoadStore1.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
29 "li $" #RT", " #RTval"\n\t" \
33 : "r" (mem1), "r" (RTval) \
37 instruction, RTval, out); \
41 "li $" #RT", " #RTval"\n\t" \
45 : "r" (mem), "r" (RTval) \
49 instruction, RTval, out); \
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
60 "li $" #RT", " #RTval"\n\t" \
65 : "r" (mem2), "r" (RTval) \
[all …]
DLoadStore.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
29 "li $" #RT", " #RTval"\n\t" \
33 : "r" (mem1), "r" (RTval) \
37 instruction, RTval, out); \
41 "li $" #RT", " #RTval"\n\t" \
45 : "r" (mem), "r" (RTval) \
49 instruction, RTval, out); \
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
60 "li $" #RT", " #RTval"\n\t" \
65 : "r" (mem2), "r" (RTval) \
[all …]
Dvfp.c49 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
56 "li $t0, " #RTval"\n\t" \
62 : "r" (mem), "r" (RTval) \
69 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
76 "li $t0, " #RTval"\n\t" \
82 : "r" (mem), "r" (RTval) \
91 #define TESTINSN5LOADw(instruction, RTval, offset, RT) \ argument
97 "li $t0, " #RTval"\n\t" \
102 : "r" (mem), "r" (RTval) \
Dmips32_dspr2.c39 #define TESTDSPINST_RD_RT_DSPC(instruction, RTval, RD, RT) \ argument
52 : "r" (RTval) \
56 RTval, dspCtrl); \
59 #define TESTDSPINST_RD_RT_NODSPC(instruction, RTval, RD, RT) \ argument
69 : "r" (RTval) \
72 printf("%s :: rd 0x%08x rt 0x%08x \n", instruction, out, RTval); \
75 #define TESTDSPINST_RD_RT_RS_NODSPC(instruction, RTval, RSval) \ argument
85 : "r" (RTval), "r" (RSval) \
89 RTval, RSval); \
92 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
[all …]
Dbranches.c114 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
128 : "r" (RSval), "r" (RTval), "r" (RDval) \
132 out, RSval, RTval); \
179 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
193 : "r" (RSval), "r" (RTval), "r" (RDval) \
197 out, RSval, RTval); \
Dmips32_dsp.c39 #define TESTDSPINST_RD_RT_DSPC(instruction, RTval, RD, RT) \ argument
52 : "r" (RTval) \
56 instruction, out, RTval, dspCtrl); \
59 #define TESTDSPINST_RD_RT_NODSPC(instruction, RTval, RD, RT) \ argument
69 : "r" (RTval) \
73 instruction, out, RTval); \
76 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
90 : "r" (RSval), "r"(RTval) \
94 instruction, RSval, RTval, out, dspCtrl); \
119 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
[all …]
DMoveIns.c238 #define TESTINSNMOVEN1s(instruction, offset, RTval, FD, FS, RT) \ argument
251 : "r" (fs_f), "r" (RTval) \
259 #define TESTINSNMOVEN1d(instruction, offset, RTval, FD, FS, RT) \ argument
273 : "r" (fs_f), "r" (RTval) \
DMIPS32int.c3 #define TESTINST1(instruction, RSval, RTval, RD, RS, RT) \ argument
13 : "r" (RSval), "r" (RTval) \
17 instruction, out, RSval, RTval); \
50 #define TESTINST3a(instruction, RSval, RTval, RS, RT) \ argument
64 : "r" (RSval), "r"(RTval) \
68 instruction, RSval, RTval, HI, LO); \
71 #define TESTINST4(instruction, RTval, RSval, RT, RS, pos, size) \ argument
80 : "r" (RTval), "r" (RSval) \
95 #define TESTINSN5LOAD(instruction, RTval, offset, RT) \ argument
100 "li $t0, " #RTval"\n\t" \
[all …]
/external/valgrind/main/none/tests/mips64/
Dload_store_multiple.stdout.exp-BE2 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
3 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
4 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
5 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
6 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
7 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
8 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
9 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1e0000
10 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
11 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
[all …]
Dload_store_multiple.stdout.exp-LE2 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
3 sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
4 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27
5 sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027
6 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff
7 sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff
8 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
9 sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00
10 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
11 sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
[all …]
Dmacro_int.h1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \ argument
11 : "r" (RSval), "r" (RTval) \
16 (long long) RTval); \
51 #define TEST4(instruction, RSval, RTval, RS, RT) \ argument
64 : "r" (RSval), "r"(RTval) \
68 instruction, (long long) RSval, (long long) RTval, HI, LO); \
71 #define TEST5(instruction, RSval, RTval, RS, RT) \ argument
84 : "r" (RSval), "r"(RTval) \
88 instruction, (long long) RSval, (long long) RTval, HI, LO); \
Dload_store_multiple.c23 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
28 "li $"#RT", "#RTval "\n\t" \
32 : "r" (mem1), "r" (RTval) \
36 instruction, RTval, out); \
40 "li $"#RT", " #RTval "\n\t" \
44 : "r" (mem), "r" (RTval) \
48 instruction, RTval, out); \
53 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
59 "li $"#RT", "#RTval "\n\t" \
64 : "r" (mem2), "r" (RTval) \
[all …]
Dcvm_ins.c85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ argument
95 : "r" (RSVal), "r" (RTval) \
99 instruction, out, RSVal, RTval); \
Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
146 : "r" (RSval), "r" (RTval), "r" (RDval) \
150 out, RDval, RSval, RTval); \
201 #define TESTINST4l(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
217 : "r" (RSval), "r" (RTval), "r" (RDval) \
221 out, RDval, RSval, RTval); \
Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
123 : "r" (RSval), "r" (RTval), "r" (RDval) \
127 out, (long long) RSval, (long long) RTval); \
Dmove_instructions.c139 #define TEST4(instruction, offset, RTval, FD, FS, RT) \ argument
151 : "r" (reg_val_f), "r" (RTval) \
158 #define TEST4d(instruction, offset, RTval, FD, FS, RT) \ argument
170 : "r" (reg_val_f), "r" (RTval) \
Dbranches.stdout.exp76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6
93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6
246 --- BEQL --- if RSval == RTval then out = RDval + 4 else out = RDval + 6
382 --- BNEL --- if RSval != RTval then out = RDval + 4 else out = RDval + 5
Dbranch_and_jump_instructions.stdout.exp515 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6
634 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6