| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 358 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
364 std::reverse(RVLocs.begin(), RVLocs.end()); in AnalyzeReturnValues()
529 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
537 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
540 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
546 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
547 CCValAssign &VA = RVLocs[i]; in LowerReturn()
721 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
723 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
725 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1064 const SmallVectorImpl<CCValAssign> &RVLocs, in LowerCallResult() argument
1069 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
1070 const CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1130 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1133 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCCCCallTo()
1235 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1445 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1446 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
1467 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1471 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2028 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2029 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); in FinishCall()
2033 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2036 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2041 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2042 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2044 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2045 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2050 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
2051 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
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| D | ARMISelLowering.cpp | 1258 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1260 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerCallResult()
1266 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1267 CCValAssign VA = RVLocs[i]; in LowerCallResult()
1285 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1299 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1303 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
2040 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2041 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
2086 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 190 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
194 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerReturn_32()
205 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_32()
206 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
250 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
254 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerReturn_64()
267 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_64()
268 CCValAssign &VA = RVLocs[i]; in LowerReturn_64()
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
936 SmallVector<CCValAssign, 16> RVLocs; in LowerCall_32() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 322 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
326 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
335 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
336 CCValAssign &VA = RVLocs[i]; in LowerReturn()
373 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
376 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
381 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
383 RVLocs[i].getLocReg(), in LowerCallResult()
384 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 3057 SmallVector<CCValAssign, 16> RVLocs; in DoSelectCall() local
3058 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, in DoSelectCall()
3062 for (unsigned i = 0; i != RVLocs.size(); ++i) { in DoSelectCall()
3063 EVT CopyVT = RVLocs[i].getValVT(); in DoSelectCall()
3069 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
3070 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
3071 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { in DoSelectCall()
3080 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
3081 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
3084 if (CopyVT != RVLocs[i].getValVT()) { in DoSelectCall()
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| D | X86ISelLowering.cpp | 1853 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1855 RVLocs, Context); in CanLowerReturn()
1873 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1875 RVLocs, *DAG.getContext()); in LowerReturn()
1886 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
1887 CCValAssign &VA = RVLocs[i]; in LowerReturn()
2043 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2046 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerCallResult()
2050 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
2051 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2612 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2614 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
2622 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2623 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2624 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
2628 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) in LowerCallResult()
2629 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); in LowerCallResult()
2796 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2798 RVLocs, Context); in CanLowerReturn()
2810 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1320 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1321 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); in finishCall()
1323 CCValAssign &VA = RVLocs[0]; in finishCall()
1324 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1410 SmallVector<CCValAssign, 16> RVLocs; in SelectCall() local
1411 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context); in SelectCall()
1413 if (RVLocs.size() > 1) in SelectCall()
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| D | PPCISelLowering.cpp | 3524 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
3526 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
3530 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
3531 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
4753 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
4755 RVLocs, Context); in CanLowerReturn()
4766 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
4768 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
4775 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
4776 CCValAssign &VA = RVLocs[i]; in LowerReturn()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1285 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
1286 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); in FinishCall()
1290 if (RVLocs.size() != 1) in FinishCall()
1294 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
1298 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
1299 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
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| D | AArch64ISelLowering.cpp | 1922 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1924 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
1928 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1929 CCValAssign VA = RVLocs[i]; in LowerCallResult()
2475 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
2476 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
2489 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
2491 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
2497 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); in LowerReturn()
2499 CCValAssign &VA = RVLocs[i]; in LowerReturn()
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